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Source—Drain contact resistance in CMOS with self-aligned TiSi 2

1987; Institute of Electrical and Electronics Engineers; Volume: 34; Issue: 3 Linguagem: Inglês

10.1109/t-ed.1987.22965

1557-9646

Yuan Taur, J.Y.-C. Sun, D. Moy, L.K. Wang, B. Davari, S. P. Klepner, C. Y. Ting,

Semiconductor materials and devices

The contact resistance between TiSi 2 and n + -p + source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10 -7 and 1 × 10 -6 Ω . cm 2 can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10 20 /cm 3 . Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi 2 -n + and TiSi 2 -P + interfaces.