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XPAND: an efficient test stimulus compression technique

2006; Institute of Electrical and Electronics Engineers; Volume: 55; Issue: 2 Linguagem: Inglês

10.1109/tc.2006.31

2326-3814

Subhasish Mitra, K.S. Kim,

VLSI and FPGA Design Techniques

Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and test time compared to traditional scan and significantly outperforms existing test compression tools. The XPAND technique is currently being used by several industrial designs.