Portal de Periódicos da CAPES

An 820 pin PGA for ultralarge-scale BiCMOS devices

1993; Institute of Electrical and Electronics Engineers; Volume: 16; Issue: 8 Linguagem: Inglês

10.1109/33.273690

1558-3082

Y. Hiruta, N. Hirano, Y. Yamaji, M. Mukai, Yoshiki Motoyama, R. Homma, J. Ohno, T. Sudô,

VLSI and FPGA Design Techniques

A high-pin-count, high-performance pin grid array (PGA) has been developed for future ASIC devices using half-micron BiCMOS technology and having a maximum usable gate count of 300k. The package has been designed with due consideration of all package functions, electrical, thermal, and mechanical. A surface mount type pin joint was adopted to realize high wiring density on the printed wiring board. The package has 820 pins with a 50-mil pitch and five rows. A highly accurate tape automated bonding (TAB) technology was applied to the die assembly to achieve narrow pitch and high pad count for the bonding between the die and the package. The thermal resistance from the die to the ambient is lower than 1.5 degrees C/W at 1 m/s air flow velocity. The electrical parameters of the package were quantified. The high reliability of the package and surface mount type soldering has been confirmed. >