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An insulator-lined silicon substrate-via technology with high aspect ratio

2001; Institute of Electrical and Electronics Engineers; Volume: 48; Issue: 9 Linguagem: Inglês

10.1109/16.944215

1557-9646

J.H. Wu, Jörg Scholvin, Jesús A. del Alamo,

Copper Interconnects and Reliability

We have developed a novel high-aspect ratio substrate-via technology in silicon that features a SiN insulator liner. In this technology, the via is completely filled with electroplated Cu. We have demonstrated vias with an aspect ratio of 30 and we have verified the integrity of the liner in vias with an aspect ratio of 8. The impedance of individual vias was measured in the microwave regime using a high-frequency test structure. The measured inductance of vias with aspect ratios between 3 and 30 approach the theoretically expected values.