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New architecture for an AES-EBU digital audio receiver

1997; Institute of Electrical and Electronics Engineers; Volume: 43; Issue: 3 Linguagem: Inglês

10.1109/30.628696

1558-4127

M. Angelici, M. Bianchessi, S.D. Feste, N. Serina,

Embedded Systems Design Techniques

This paper describes the realization of a digital audio receiver in accordance with the AES3 and S/PDIF format. It illustrates its realization and the performance obtained in terms of output jitter measured on the test chip. This receiver is realized in 3-metal layer 0.5 /spl mu/m CMOS technology, and with a 3.3 V power supply. This low power supply makes the interface compatible with the new generation of VLSI circuits, although it increases the analog design difficulties.