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A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution

1994; Institute of Electrical and Electronics Engineers; Volume: 29; Issue: 3 Linguagem: Inglês

10.1109/4.278359

1558-173X

C. Thomas Gray, Wentai Liu, Wilhelmus Van Noije, Thomas A. Hughes, Ralph K. Cavin,

Low-power high-performance VLSI design

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution. >