Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's
1994; Institute of Electrical and Electronics Engineers; Volume: 15; Issue: 9 Linguagem: Inglês
10.1109/55.311136
ISSN1558-0563
AutoresL.T. Su, J.B. Jacobs, J.E. Chung, D.A. Antoniadis,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoShort-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices.
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