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A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop

1999; Institute of Electrical and Electronics Engineers; Volume: 34; Issue: 12 Linguagem: Inglês

10.1109/4.808901

1558-173X

A. Namdar, Bosco Leung,

Radio Frequency Integrated Circuit Design

A 0.8-/spl mu/ BiCMOS, 400-MHz intermediate-frequency digitizer based on embedding a down-conversion mixer inside a sigma-delta modulator together with a reconstruction filter in the feedback path has been developed. The digitizer, when subsampled with a clock of 20 MHz, achieves a measured resolution of 12 bits for a 40-kHz bandwidth and dissipates 18 mW of power. The third harmonic distortion (HD/sub 3/) is less than -90 dBc for a -4-dB input, and the third-order intermodulation product (IM/sub 3/) is less than -70 dBc for a -8-dB input, with a full-scale voltage of 0.5 V. The chip area is 1.5 mm/sup 2/.