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Quadrature sampling schemes with improved image rejection

2003; Institute of Electrical and Electronics Engineers; Volume: 50; Issue: 9 Linguagem: Inglês

10.1109/tcsii.2003.816927

1558-125X

Kong‐Pang Pun, J.E. Franca, Carlos Azeredo-Leme, Roberto dos Reis,

Advancements in PLL and VCO Technologies

A fundamental problem of analog quadrature sampling circuits is the in-phase/quadrature-phase (I/Q) mismatch, which adversely affects their image rejection performance. This brief proposes two new quadrature sampling circuits for the sampling of complex intermediate frequency signals with high image rejection performance. The first circuit reduces the I/Q mismatches by time-sharing of the sampling capacitors and by employing a special clocking scheme. The second circuit integrates a first-order complex notch filter to provide extra image rejection. Both circuits are very simple and they introduce little overhead compared with conventional circuits. Circuit simulations show that for 2% channel mismatch, the first circuit removes completely the image interferer, and the second one achieves over 70 dB of image rejection ratio in a narrow band around direct current, while the conventional circuits achieve only about 40 dB.