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Three-dimensional table look-up MOSFET model for precise circuit simulation

1982; Institute of Electrical and Electronics Engineers; Volume: 17; Issue: 3 Linguagem: Inglês

10.1109/jssc.1982.1051758

1558-173X

T Shima, Tsutomu Sugawara, Seijiro Moriyama, Hisashi Yamada,

VLSI and FPGA Design Techniques

A three-dimensional table look-up MOSFET modeling technique is described. The table, which is able to deal with future submicron devices, is constructed with a few thousand work memory capacity requirement by suppressing data redundancy. Sufficiently high accuracy, with less than point several percent error, is achieved by using a special interpolation, which is called curve shape fitting technique. Computational time to perform the interpolation from the table is much less than that for the analytical model.