A novel simplified process for fabricating a very high density p-channel trench gate power MOSFET
2000; Institute of Electrical and Electronics Engineers; Volume: 21; Issue: 7 Linguagem: Inglês
10.1109/55.847382
ISSN1558-0563
AutoresKee Soo Nam, Ju Wook Lee, Sang‐Gi Kim, Tae Moon Roh, Hoon Soo Park, Jin Gun Koo, Kyung Ik Cho,
Tópico(s)Advancements in Semiconductor Devices and Circuit Design
ResumoA novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch 2 ) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 m/spl Omega/-cm 2 with a breakdown voltage of -36 V.
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