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A 3-ns 1-kbit RAM using super self-aligned process technology

1981; Institute of Electrical and Electronics Engineers; Volume: 16; Issue: 5 Linguagem: Inglês

10.1109/jssc.1981.1051617

1558-173X

T. Sakai, Y. Yamamoto, Yoshiyuki Kobayashi, K. Kawarada, Y. Inabe, Tsuyoshi Hayashi, H. Miyanaga,

Low-power high-performance VLSI design

A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.