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Pulsewidth Modulations for the Comprehensive Capacitor Voltage Balance of $n$-Level Three-Leg Diode-Clamped Converters

2009; Institute of Electrical and Electronics Engineers; Volume: 24; Issue: 5 Linguagem: Inglês

10.1109/tpel.2009.2016661

1941-0107

Sergio Busquets‐Monge, Salvador Alepuz, Joan Rocabert, J. Bordonau,

Silicon Carbide Semiconductor Technologies

In the previous literature, the introduction of the virtual-space-vector (VV) concept for the three-level, three-leg neutral-point-clamped converter has led to the definition of pulsewidth modulation (PWM) strategies, guaranteeing a dc-link capacitor voltage balance in every switching cycle under any type of load, with the only requirement being that the addition of the three phase currents equals zero. This paper presents the definition of the VVs for the general case of an n -level converter, suggests guidelines for designing VV PWM strategies, and provides the expressions of the leg duty-ratio waveforms corresponding to this family of PWMs for an easy implementation. Modulations defined upon these vectors enable the use of diode-clamped topologies with passive front-ends. The performance of these converters operated with the proposed PWMs is compared to the performance of alternative designs through analysis, simulation, and experiments.