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MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool

2015; Institute of Electrical and Electronics Engineers; Volume: 35; Issue: 1 Linguagem: Inglês

10.1109/tcad.2015.2448675

1937-4151

Dimitri Kagaris,

VLSI and FPGA Design Techniques

Transistor count minimization is an important goal as very-large-scale integration technology approaches its technical and physical limits. In this paper, we present a computer-aided design synthesis tool that tries to minimize the number of transistors required to implement a given multiple-output logic function. The proposed transistor-level synthesis approach goes beyond the traditional series-parallel design style and allows for extensive bridging. It starts from a sum-of-products expression for each output, allowing also for don't care terms, and produces a transistor network with a small number of transistors to implement all outputs jointly under a user-specified bound on the number of transistors in series to avoid long charge/discharge paths. Experimental results on previously examined multioutput functions and case studies (full adder, Gray/binary counter, and seven-segment display) demonstrate the benefit of the approach.