Reduction in number of devices for symmetrical and asymmetrical multilevel inverters
2015; Institution of Engineering and Technology; Volume: 9; Issue: 4 Linguagem: Inglês
10.1049/iet-pel.2015.0176
ISSN1755-4543
AutoresShivam Prakash Gautam, Lalit Kumar Sahu, Shubhrata Gupta,
Tópico(s)Microgrid Control and Optimization
ResumoIET Power ElectronicsVolume 9, Issue 4 p. 698-709 Research ArticlesFree Access Reduction in number of devices for symmetrical and asymmetrical multilevel inverters Shivam Prakash Gautam, Corresponding Author Shivam Prakash Gautam shivamprakashgautam@gmail.com Department of Electrical Engineering, National Institute of Technology, Raipur, 492 010 IndiaSearch for more papers by this authorLalit Kumar Sahu, Lalit Kumar Sahu Department of Electrical Engineering, National Institute of Technology, Raipur, 492 010 IndiaSearch for more papers by this authorShubhrata Gupta, Shubhrata Gupta Department of Electrical Engineering, National Institute of Technology, Raipur, 492 010 IndiaSearch for more papers by this author Shivam Prakash Gautam, Corresponding Author Shivam Prakash Gautam shivamprakashgautam@gmail.com Department of Electrical Engineering, National Institute of Technology, Raipur, 492 010 IndiaSearch for more papers by this authorLalit Kumar Sahu, Lalit Kumar Sahu Department of Electrical Engineering, National Institute of Technology, Raipur, 492 010 IndiaSearch for more papers by this authorShubhrata Gupta, Shubhrata Gupta Department of Electrical Engineering, National Institute of Technology, Raipur, 492 010 IndiaSearch for more papers by this author First published: 01 March 2016 https://doi.org/10.1049/iet-pel.2015.0176Citations: 55AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract Multilevel inverter (MLI) is receiving remarkable recognition due to its reduced voltage stress across the power switches and low total harmonic distortion in output voltage. However, MLI incorporates large number of semiconductor switches and hence increases its complexity. In this study, new structures of symmetrical and asymmetrical MLI are proposed. The proposed structures offer reduced number of controlled switches, power diodes, capacitors and DC sources as compared with classical and recently proposed topologies in the line. Reduction of switch count, driver circuit and DC voltage sources reduces the size, cost, complexity and enhances overall performance. Moreover significant reduction in voltage stress across the switches can be achieved. A comparative analysis of proposed topologies with the classical topology and recently published topologies has been made in terms of controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier pulse width modulation strategy is adopted for generating the switching pulses. The detailed simulation study of the proposed topology has been carried out using MATLAB/Simulink and feasibility of topology has been validated experimentally. 1 Introduction Multilevel inverter (MLI) was first introduced in 1975, since its invention the demand is growing rapidly in the field of DC/AC power conversion and associated applications [1]. MLI is key technology and plays crucial role in AC motor drives, uninterruptible power supplies, high-voltage DC power transmission, flexible AC transmission systems, static var compensators, active filters, electric and hybrid electric vehicles and integration and utilisation of renewable energy sources [2-14]. In the field of high-power medium-voltage DC/AC conversion, MLI is receiving tremendous popularity both in terms of topology and control scheme due to its good power quality, less total harmonic distortion (THD), reduced voltage stress across the switches, good electromagnetic compatibility, less switching losses and dv/dt stress. However, MLI possesses some drawback, that is, to increase output levels, the number of semiconductor switch requirement along with peripherals devices such as gate driver circuit, protection circuit and heat sink increases. Increased device count makes overall system complex, bulky and costly and reduces the reliability and efficiency of the converter. Traditionally, MLIs are classified as; cascaded H-bridge (CHB), flying capacitor (FC) and neutral point clamped (NPC). In the past few decades, most of the literatures published shows the study on CHB, FC and NPC topologies with respect to their respective advantages and disadvantages [15] and these topologies are now widely referred to as the ‘classical topologies’. None of the classical topologies seem to be absolutely advantageous as multilevel solutions are heavily influenced by application and component count, cost and complexity considerations. Among the classical MLI, CHB has received wide attention due to its modularity and simplicity; however, the requirement of isolated source is a limitation of the topology [16]. A CHB MLI is composed of several H-bridge cell and isolated DC source. On the basis of voltage magnitude DC source, CHB is classified as symmetric and asymmetric configurations. In symmetric configuration, the magnitude of DC source is equal (V1 = V2 = V3…), whereas in asymmetric configuration magnitudes of DC sources are not equal (V1 ≠ V2 ≠ V3….). The asymmetric configuration of CHB produces higher number of voltage level as compared with symmetric configuration for same number of power switches [15]. Along with the exploration of CHB, researchers paid dedicated effort and attention to evolve newer application oriented topologies with reduced number of device count and complexity. Consequently, in past few years, large numbers of topologies and control scheme have been proposed with reduced device count which utilises a combination of unidirectional and bidirectional switches of different ratings [15-31], some of them are reviewed here briefly. In [16-21], symmetrical topologies of MLIs are discussed, the cost of these inverters is less due to low variety of DC sources, but the modularity of these MLIs is major concern in various applications. Similarly in [22-33], asymmetrical topologies of MLI with reduced number of switches are presented, but the requirement of large number of bidirectional switches is a major issue in these topologies. Topology of MLI presented in [22] utilises low-frequency high-power switches due to which there is presence of lower-order harmonics in output waveform which is the major drawback. In [23, 24], topology incorporates multi-winding transformer due to which cost and complexity of the overall topology increases. A 4-level inverter topology is presented in [25], but the presented topology is unable to provide zero-voltage level which results in high root mean square value and harmonic energy is concentrated at switching frequency. In [28], another topology is presented for 5-level by utilising four DC sources, whereas in conventional topologies up to 9-level can be reached by utilising four DC sources. The topology presented in [32, 33] also reduces the number of controlled switches to a great extent for both symmetrical and asymmetrical MLIs, but the requirement of large number of isolated DC sources is the major drawback of these topologies. Existing literature reflects that most of the published MLI topologies in recent years are claiming higher outputs levels with reduced number of switches. However, great compromise has been made in terms of modularity, simplicity, number of bidirectional switches, variety of DC sources, voltage stress across switches, reliability and losses. This paper focuses on symmetrical and asymmetrical MLI topologies and tries to solve the problems related to it. Two new topologies of symmetrical and asymmetrical MLIs are proposed using hexagon switch cell (HSC). The proposed topology is capable of producing 7/9/11 output levels by utilising seven controlled switches. Reduction of devices is based on reduction in number of insulated gate bipolar transistors (IGBTs), driver circuits, diodes, bidirectional switches, DC sources and heat sinks. The symmetrical and asymmetrical configurations of proposed topologies generate higher number of output levels with less number of switches comparatively. Qualitative improvement is based on reduction in blocking voltages on switches, variety of switches, variety of heat sinks, equal utilisation of DC sources and improvement in fault tolerance capability of inverter. An exhaustive comparison of proposed topologies with classical topologies and most recent work in the field is carried out to highlight the novelty and benefit of the proposed topology. The organisation of this paper is as follows: in Section 2, the Proposed-I and Proposed-II topologies of MLI for symmetrical and asymmetrical configurations are explained and its working is given. Section 3 deals with the simulation and experimental results of the proposed topologies. Section 4 gives the comparison of both symmetrical and asymmetrical topology to the earlier presented topologies. Finally, conclusion is given in Section 5. 2 Proposed MLI topologies 2.1 Proposed topology-I The configuration of Topology-I is illustrated in Fig. 1a. It consists of two DC voltage sources , along with capacitors C1 and C2 which forms voltage divider circuit. An auxiliary switch is formed by controlled switch S7 and four diodes D7, D8, D9 and D10 which is connected to HSC composed by six switches S1, S2, S3, S4, S5 and S6. When the values of the DC voltage sources are equal, that is, then it can be referred as symmetrical MLI otherwise asymmetrical. Topology-I is capable of producing 7-/9-/11-level output with certain combination of DC voltage source while incorporating only seven controlled switches. The output voltage level with particular combination of DC voltage source is summarised in Table 1. The generalised form of the proposed Topology-I is shown in Fig. 1b. Table 1. Different combinations of DC voltage source for higher output voltage levels Algorithm Values of DC sources Number of output levels Configuration first 7 asymmetrical second 9 symmetrical third 11 asymmetrical Fig. 1Open in figure viewerPowerPoint Proposed topology-I a Configuration of proposed Topology-I for 9-level inverter b Generalised configuration of proposed Topology-I To evaluate total number of component count, the Topology-I is compared with classical topologies for 9-level output and summarised in Table 2. Table 2. Comparison of different 9-level inverter topologies for symmetrical MLI Components Proposed Topology-I NPC FC CHB main power switches 6 16 16 16 auxiliary switch 1 0 0 0 diodes 10 72 16 16 capacitors 2 8 36 — Main power switches: The proposed Topology-I in symmetrical configuration achieves 56.25% (seven instead of 16) reduction in the number of main power switches required as compared with classical topologies. Power diodes: The proposed Topology-I in symmetrical configuration achieves 37.5% (10 instead of 16) reduction in the number of diodes required as compared with FC and CHB, whereas percentage of reduction increases to 86.11% (10 instead of 72) as compared with NPC. Similarly, it achieves 74% (2 instead of 8) reduction in number of capacitors required when compared with the NPC and 94.44% (2 instead of 36) reduction when compared with the FC. The different operating modes and switching states along with corresponding output voltage levels for 9-level inverter are summarised in Fig. 2 and Table 3, respectively. Similarly, the different switching states of Topology-I in asymmetrical configuration for synthesising 7-level and 11-level are summarised in Tables 4 and 5, respectively. The generalisation of Topology-I in symmetrical configuration for N-level output is given as (1) (2) (3) (4) Table 3. Different switching states of Topology-I for 9-level output Output levels, V ‘ON’ state switches Conducting diodes 1 S4, S7 D6, D7, D10 2 S4, S5 D2 3 S4, S5, S7 D7, D10 4 S1, S4, S5 – 0 – – −1 S3, S7 D5, D8, D9 −2 S3, S6 D1 −3 S3, S6, S7 D8, D9 −4 S2, S3, S6 – Table 4. Different switching states of Topology-I for 7-level output Output levels, V ‘ON’ state switches Conducting diodes 1 S4, S7 D6, D7, D10 2 S1, S4 D6 3 S1, S4, S5 – 0 – – −1 S3, S7 D5, D8, D9 −2 S2, S3 D5 −3 S2, S3, S6 – Table 5. Different switching states of Topology-I for 11-level output Output levels, V ‘ON’ state switches Conducting diodes 1 S4, S7 D6, D7, D10 2 S1, S4 D6 3 S4, S5 D2 4 S4, S5, S7 D7, D10 5 S1, S4, S5 – 0 – – −1 S3, S7 D5, D8, D9 −2 S2, S3 D5 −3 S3, S6 D1 −4 S3, S6, S7 D8, D9 −5 S2, S3, S6 – Fig. 2Open in figure viewerPowerPoint Different operating modes of Topology-I for 9-level output 2.2 Proposed Topology-II The configuration of the proposed Topology-II is shown in Fig. 3a. It is modification of Topology-I in the light of generalisation for symmetric and asymmetric configurations. Topology-II is composed of two auxiliary switches connected to HSC from both the sides. The composed switch network is supplied by two DC voltage source along with four capacitors. The generalised structure of Topology-II is illustrated in Fig. 3b. It contains series connection of several fundamental cells that can be operated for both symmetrical and asymmetrical configurations. Each cell contains eight controlled switches, 14 power diodes, two DC sources and four capacitors. The DC source on the left-hand side of HSC is numbered as and on the right-hand side of HSC is numbered as (‘where n denotes number of series cell’). For symmetrical mode, the values of DC sources are equal and for asymmetrical mode the values of each DC sources are assigned according to the three different algorithms given in Table 6. In conventional asymmetrical CHB MLI values of DC sources are increased in either binary combination (2:1) or ternary combination (3:1). In recently published work of asymmetrical configuration of MLI expanded the voltage ratio as 4:1 in [30], 5:1 in [30] and 7:1 in [31]. The increase in ratio of DC voltage source above the ternary combination opens the possibility of achieving higher number of output level with reduced number of switches in asymmetrical configuration. The different combinations of DC voltage source and corresponding output levels are summarised in Table 6. Therefore, in the Topology-II a new algorithm of DC source combination (fourth algorithm in Table 6) is opted to achieve the higher number of output levels (5) (6) (7) (8) Table 6. Realisation of different levels from proposed-II topology incorporating ‘n’ number of cells Algorithm Values of DC sources Number of output levels Configuration first 8 × n + 1 symmetrical second asymmetrical third asymmetrical fourth asymmetrical Fig. 3Open in figure viewerPowerPoint Proposed Topology-II a Configuration of proposed Topology-II b Generalised structure of proposed Topology-II The different switching states of 9-level (symmetrical) and 17-level (asymmetrical) are presented in Tables 7 and 8, respectively. Table 7. Output voltage and corresponding switches states for 9-level Proposed-II symmetric topology Output levels, V ‘ON’ state switches Conducting diodes 1 S4, S7 D6, D7, D10 2 S1, S4 D6 3 S1, S4, S8 D13, D14 4 S1, S4, S5 – 0 – – −1 S3, S7 D5, D8, D9 −2 S2, S3 D5 −3 S2, S3, S8 D12, D13 −4 S2, S3, S6 – Table 8. Output voltage and corresponding switches states for 17-level Proposed-II symmetric topology Output levels, V ‘ON’ state switches Conducting diodes 1 S4, S7 D6, D7, D10 2 S1, S4 D6 3 S4, S8 D2, D11, D14 4 S4, S7, S8 D7, D10, D11, D14 5 S1, S4, S8 D11, D14 6 S4, S5 D2 7 S4, S5, S7 D7, D10 8 S1, S4, S5 – 0 – – −1 S3, S7 D5, D8, D9 −2 S2, S3 D5 −3 S3, S8 D1, D12, D13 −4 S3, S7, S8 D8, D9, D12, D13 −5 S2, S3, S8 D12, D13 −6 S3, S6 D1 −7 S3, S6, S7 D8, D9 −8 S2, S3, S6 – 3 Simulation and experimental results 3.1 Modulation scheme Multi-carrier pulse width modulation (MCPWM) technique has been employed with carrier frequency of 100 Hz, whereas reference signal frequency is kept at 50 Hz. In MCPWM scheme, carrier signals are compared with reference signal and pulses so obtained are used for switching of devices corresponding to their respective voltage levels. Number of carrier increases as the number of levels increases and the increment is directly proportional. Basic strategy for MCPWM is given in Fig. 4a. Gate pulses for 9-level proposed Topology-I is shown in Fig. 4b. Fig. 4Open in figure viewerPowerPoint Basic strategy for MCPWM a Modulation strategy for 9-level proposed-I inverter b Gate pulses for 9-level proposed-I inverter Here in one cycle, reference signal is divided into nine different modes (9) (10) (11) (12) (13) (14) (15) (16) (17)By using logical operators switching pulses for switches can be obtained as (18) (19) (20) (21) (22) (23) (24) 3.2 Simulation results To examine the performance of the proposed topologies simulation has been carried out using MATLAB/Simulink. Topology-I is simulated for symmetrical and asymmetrical configurations as 9-level and 11-level inverters, respectively. The simulation result for 9-level and 11-level inverters and their corresponding THD is shown in Figs. 5a and b. Topology-II is simulated in asymmetrical configuration to obtain 17-level and 257-level outputs. The simulation result for 17-level and 257-level inverters and their corresponding THD is shown in Figs. 5c and d. Capacitor voltages of Topologies I and II have been shown in Figs. 6a and b, respectively. Different simulation parameters for Topology-I and Topology-II are given in Table 9. A comparison of THD obtained for both Topology-I and Topology-II has been presented in Table 10. Table 9. Simulation parameters Parameters Topology-I 9-level Topology-I 11-level Topology-II 17-level Topology-II 257-level Source-I 2 V 2 V 2 V Source-II 2 V 3 V 6 V capacitor, µF 1100 1100 1100 1100 R, Ω 50 50 10 10 L, mH 10 10 5 5 switching frequency, Hz 100 100 100 100 Table 10. Analysis of THD for 9-/11-/17-/257-level inverters MLI topology Controlled switches Output levels Simulated THD, % Topology-I symmetric 7 9 12.03 Topology-I asymmetric 7 11 8.67 Topology-II asymmetric 8 17 6.06 Topology-II asymmetric 16 257 0.48 Fig. 5Open in figure viewerPowerPoint Simulation result for topology-I and topology-II a 9-Level Output Voltage and corresponding THD b 11-Level Output Voltage and corresponding THD c 17-Level Output Voltage and corresponding THD d 257-Level Output Voltage and corresponding THD Fig. 6Open in figure viewerPowerPoint Capacitor voltages of Topologies I and II a Capacitor voltages of 9-level symmetrical inverter of Topology-I b Capacitor voltages of 17-level asymmetrical inverter of Topology-II 3.3 Experimental results To validate the concept and ensure the feasibility of the proposed topologies, an experimental setup of the proposed 9-level and 17-level inverters has been developed and validated experimentally. dSPACE DS1103 real-time digital controller has been used for generating switching pulses. To provide DC voltages for 9-level inverter, two identical 24 V batteries are used for input voltage and for 17-level inverter two batteries of 10 and 30 V are used. All the experimental parameters for Topologies I and II are given in Table 11, respectively. All the waveforms are measured and recorded with the help of power quality analyser (Fluke 434-II) and Tektronix TPS2014 four channel oscilloscope. The experimental result for 9-level and 17-level inverters and their corresponding THD is shown in Figs. 7a and b, respectively. Fig. 7a shows the output waveforms of 9-level inverter along with its capacitors voltage. Fig. 7b depicts the waveform of 17-level asymmetrical topology along with its four capacitor voltages. From Fig. 7, it is concluded that all the capacitors in the proposed topologies have balanced voltage. Experimental setup consists of various equipments such as Fluke 434-II power quality analyser, Tektronix TPS2014 four channel oscilloscope, batteries, dSPACE1103, workstation, discrete IGBT power module with inbuilt driver and protection circuit. Table 11. Experimental parameters Parameters Topology-I 9-level Topology-II 17-level Source-I 24 V 10 V Source-II 24 V 30 V capacitor, µF 1100 1100 R, Ω 25 25 L, mH 5 5 switching frequency, Hz 100 100 Fig. 7Open in figure viewerPowerPoint Experimental result for 9-level and 17-level inverters and their corresponding THD a 9-Level experimental output waveform along with its capacitors voltage and its corresponding THD b 17-Level experimental output waveform along with its capacitors voltage 4 Comparison study 4.1 Comparison for symmetrical MLI It is to noted that the Topology-I in symmetrical configuration requires the least amount of switches to generate particular output levels as compared with cascaded version of Topology-I and others topologies. A comparison based on number of output levels versus number of IGBT required is made between proposed Topology-I and topologies presented in [17-21, 31] and plotted in Fig. 8a. Similarly, the number of diode required in Topology-I is less as compared with [17, 18, 20, 31] and cascaded Topology-I and equals to topologies presented in [19, 21] as shown in Fig. 8b. In addition, number of DC sources required is significantly less as compared with the recently proposed topologies as depicted in Fig. 8c. It can be observed that the proposed Topology-I produces higher number of output levels with reduced number of part count. Fig. 8Open in figure viewerPowerPoint Comparison for symmetrical MLI a Number of output levels versus the number of IGBTs b Number of output levels versus the number of diodes c Number of output levels versus the number of DC sources d Number of components required for symmetrical MLI versus output levels In comparison of proposed topologies with existing topologies, it can be observed that Topology-I offers less number of switches, driver circuit, diodes and DC sources requirement. Consequently, cost, complexity and size of the Topology-I is reduced. However, the main drawback of Topology-I is that two of its switches limit its high-voltage applications. It is to noted here that the same problem occurs in topologies presented in [17-20, 24, 26, 30, 33] where four switches have to bear the full rated voltage which limits their applications for high-voltage applications, whereas in Topology-I the number of switches that need to bear the full rated voltage has been reduced to two, but still the problem remains unsolved. Hence the solution is provided in Topology-II where the cascaded connection of Topology-I is used. Hence it depends on type of application, for low-to-medium-voltage application Topology-I is best suited, whereas in high-voltage application cascaded version of Topology-I is preferred. Moreover, DC source requirement is best among the other compared topologies, and hence offers reduced cost and complexity. The detailed summary of comparison is presented in Fig. 8d and Table 12 where ‘N’ denotes number of output levels. Table 12. Components requirements for single-phase symmetrical MLI Components MLI type Topology-I Cascaded-I NPC FC CHB [17] [18] [19] [20] [21] [31] main switches (N + 19)/4 7(N − 1)/8 2(N − 1) 2(N − 1) 2(N − 1) (N + 5)/2 (N + 3) (N + 5)/2 (N + 1) (N + 1) 3(N − 1)/2 main diodes (N + 1) 5(N − 1)/2 2(N − 1) 2(N − 1) 2(N − 1) 2(N − 1) (N + 3) (N + 5)/2 (N + 1) (N + 1) 3(N − 1)/2 clamping diodes 0 0 (N − 1) × (N − 2) 0 0 0 0 (N − 3)/2 (N − 3)/2 0 0 DC bus capacitor/isolated supply (N + 7)/4 (N − 1)/2 (N − 1)/3 (N − 1)/3 (N − 1)/2 (N + 1)/2 (N − 1)/2 (N − 1)/2 (N − 1)/2 (N − 1)/2 (N − 1)/2 FC 0 0 0 (N − 1) × (N − 2)/2 0 0 0 0 0 0 0 total (3/2)(N + 5) (21/8)(N − 1) (N − 1) × (3N + 7)/3 (N − 1) × (3N + 20)/3 (9/2) × (N − 1) (3N + 1) (5N + 11)/2 (2N + 3) 3N (5N + 3)/2 7(N − 1)/2 4.2 Comparison for asymmetrical MLI In asymmetrical configuration, the proposed Topology-II is compared with existing topologies of asymmetrical configuration. From Fig. 9a, it can be observed that the Topology-II requires least number of IGBTs as compared with CHB (ternary combination) and topologies presented in [26, 27, 30, 31] over a particular output levels. Similarly, the number of diodes required in Topology-II is less as compared with [27, 30] and more with respect to CHB and topologies presented in [26, 31] as shown in Fig. 9b. In addition, number of DC sources required is less as compared with CHB and the topologies presented in [26, 27, 31], but more with respect to [30] as depicted in Fig. 9c. Fig. 9Open in figure viewerPowerPoint Comparison for asymmetrical MLI a Number of output levels versus the number of IGBTs b Number of output levels versus the number of diodes c Number of output levels versus DC sources In Topology-II, the number of switches and driver circuits are least as compared with other topologies. Moreover, DC source requirement is second best among the other compared topologies, and hence offers reduced cost and complexity. 4.3 Loss analysis Conduction losses: Calculation of losses is very essential part of the system design. MLI undergoes three modes of operation and they are blocking mode, conduction mode and switching mode. In blocking mode, the devices have to withstand the voltage across its terminal; hence no current will flow in this mode across the device due to which the losses in this mode are considered to be negligible. Hence majority of the losses in MLI are in conduction and switching mode. Conduction mode is described as the amount of power lost when the device is in ‘ON’ state. In this paper, both diodes and transistors are used for generating output levels; hence, conduction losses for both the devices are shown. First conduction losses for individual devices are calculated and then generalised for the proposed MLI. Losses of the devices at any instant ‘t’ is defined by (25) (26)where CT(t) and CD(t) are conduction losses of transistor and diodes, respectively. VT and VD are the ON state voltages of transistor and diodes. RT and RD are equivalent forward resistance of transistor and diodes. ‘β’ is a constant depending on the material used for transistor. Conduction losses are proportional to number of devices that are ‘ON’ at a particular level. Hence conduction losses for each level can be calculated by adding all the conduction losses at each level. In worst case only three IGBTs and two diodes are ‘ON’ and in best case two IGBTs and one diode are ‘ON’ in the proposed Topology-I for 9-level compared with eight IGBTs ‘ON’ in conventional 9-level CHB. Hence conduction losses are reduced by more than 50% for the proposed Topology-I when compared with conventional CHB. Moreover, as the number of switches conduct at a particular level is lower than CHB hence it has better efficiency, whereas in [18, 19] five switches conduct and in [21] ten switches conduct, hence proposed Topology-I has better efficiency as compared with above-mentioned topologies. Switching losses: Switching losses depend on number of switching transition, that is, transition from ‘ON’ to ‘OFF’ and transition from ‘OFF’ to ‘ON’. Hence it depends on modulation method. At first, switching losses are calculated for individual IGBT and then extended for whole topology. Linear approximation of voltage and current is used for loss calculation. Mathematical expression for calculation of energy loss during turn-off period is (27)where Eoff, i is the energy loss of the ‘ith’ switch, VB, i is the blocking voltage of the ‘ith’ switch, I is the current through the ‘ith’ switch before turning off and toff is the turn-off time of the ‘ith’ switch. Similarly, the mathematical expression for calculation of energy loss during turn-on period is (28)where Eon, i is the energy loss of the ‘ith’ switch, VB, i is the blocking voltage of the ‘ith’ switch, I′ is the current through the ‘ith’ switch after turning ON and ton is the turn-on time of the ‘ith’ switch. Hence, if assuming I = I′, the total switching power losses for individual switch can be calculated as (29)where fs is the switching frequency of the ‘ith’ switch and Ploss, i is the power loss for the ‘ith’ switch. From (29) it is clear that (30)As earlier discussed that the blocking voltage of the H-bridge switches used in [17-20, 24, 26, 30, 33–35] has been reduced to half in Proposed-I topology, hence from (30) it is very clear that the switching losses of the switches of H-bridge reduces to half of hexagonal cell in Proposed-I topology. To compare the switching losses of 9-level symmetrical CHB with that of 9-level proposed Topology-I, (29) can be written as (31)Assuming that ton and toff are of same period and they carry same current I, (31) can be written as (32)where c = (1/6) × I × (ton + toff) is a constant, thus from (20) switching losses for 9-level symmetrical CHB having voltage source VDC can be written as (33)Now in the proposed Topology-I there is one IGBT with blocking voltage of VDC, four IGBTs with blocking voltage 2 × VDC and two IGBTs with blocking voltage 4 × VDC. The two IGBTs with blocking voltage 4 × VDC are switched only once during a fundamental cycle as discussed earlier. Let the switching frequency be denoted by fs and fundamental frequency be denoted by fo. Then by using (20), switching losses for 9-level proposed inverter-I having voltage source of 2 VDC can be written as (34) (35)Since ((9/8) × fs ≫ fo), (23) can be written as (36)From (33) and (36) (37)Hence from (37) it is clear that the switching losses of the 9-level proposed inverter-I are almost half as that of 9-level symmetrical CHB under similar operating conditions. 5 Conclusion In this paper, two novel topologies of symmetrical and asymmetrical configurations of MLI are proposed. For wide range of application (i.e. medium-to-high voltage), Topology-I has been modified to cascaded version of Topology-I. To get maximum levels at output, again Topology-I has been modified to Topology-II and its operation is explained. First, the topology in symmetrical configuration is presented and a comparison is drawn for 9-level inverters. Then asymmetrical version of the proposed Topology-II is given along with its operating states. The proposed topologies reduce the number of controlled switches, diodes, DC voltage sources and capacitor significantly when compared with conventional ones and other topologies presented recently. A wide range of comparison is made between the proposed topology and some of the recent published topology. The comparison shows that the minimum number of IGBTs, diodes, capacitors and blocking voltage of switches to maximum number of levels for output voltage is obtained. Finally, the proposed topologies have been verified through simulation and electrical feasibility has been tested experimentally. 6 References 1Baker R.H., and Bannister L.H.: ‘ Electric power converter’. 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