Fixed‐frequency adaptive off‐time controlled buck current regulator with excellent pulse‐width modulation and analogue dimming for light‐emitting diode driving applications
2015; Institution of Engineering and Technology; Volume: 8; Issue: 11 Linguagem: Inglês
10.1049/iet-pel.2014.0969
ISSN1755-4543
AutoresYanming Li, Tong Qian, Xiaobing Yang, Kaikai Wu, Hong Chai, Changbao Wen, Yanzhang Qiu,
Tópico(s)GaN-based semiconductor devices and materials
ResumoIET Power ElectronicsVolume 8, Issue 11 p. 2229-2236 Research ArticlesFree Access Fixed-frequency adaptive off-time controlled buck current regulator with excellent pulse-width modulation and analogue dimming for light-emitting diode driving applications Yan-Ming Li, Corresponding Author Yan-Ming Li [email protected] School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorQian Tong, Qian Tong School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorXiao-Bing Yang, Xiao-Bing Yang School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorKai-Kai Wu, Kai-Kai Wu School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorHong Chai, Hong Chai School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorChang-Bao Wen, Chang-Bao Wen School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorYan-Zhang Qiu, Yan-Zhang Qiu School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this author Yan-Ming Li, Corresponding Author Yan-Ming Li [email protected] School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorQian Tong, Qian Tong School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorXiao-Bing Yang, Xiao-Bing Yang School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorKai-Kai Wu, Kai-Kai Wu School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorHong Chai, Hong Chai School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorChang-Bao Wen, Chang-Bao Wen School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this authorYan-Zhang Qiu, Yan-Zhang Qiu School of Electronic and Control Engineering, Chang'an University, Xi'an, Shaanxi, People's Republic of ChinaSearch for more papers by this author First published: 01 November 2015 https://doi.org/10.1049/iet-pel.2014.0969Citations: 4AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Abstract This study presents an ideal synchronous buck current regulator for variety of light-emitting diode (LED) loads from wide input voltage range. By using high-side power switch matched sense, the regulator maintains high current accuracy and high system efficiency. The adjustable current sense threshold provides a full-range analogue dimming and the fast output enable/disable function allows for high-frequency pulse-width modulation (PWM) dimming. In addition, the two dimming methods are easy to implement and have highly linear range. An adaptive off-time control is adopted to regulate an accurate constant current for its fast response and no need for control loop compensation, while its disadvantage of variation of switching frequency is overcome. The proposed circuit has been fabricated with 0.35 μm 40 V bipolar-CMOS-DMOS (BCD) process successfully. The experimental results confirm that the LED driver can operate within 6–40 V input voltage, and can drive a 1–10 output series connected LEDs. The switching frequency is fixed at 500 kHz with a variation of ±2%. The measured system peak efficiency is up to 95% at 1 A LED current and 10 V output voltage. The settling time at the PWM rising edge is <3.5 μs which is well beneficial for fast PWM dimming. 1 Introduction Currently, the light-emitting diode (LED), characterised by energy saving, low cost, long life and small size, is expected to be the most promising next-generation lighting source [1-3]. It has been used in broad applications such as lighting systems, backlighting devices and automotive electronics. In recent years, LED driver technique has been a hot research topic in power electronics applications, and the studies mainly focus on high efficiency [4-9], dimming techniques [5, 6, 10-15], high power [7, 16], wide range of input and output voltage [6, 16, 17] and so on. To improve the efficiency, some low-power LED current sampling methods have been discussed in the literature [18-21], but there is a trade-off between the power consumption and the sampling accuracy. In the existing control methods, constant on-time and constant off-time (COFT) control can trigger continuous on-time or off-time switching period when the load or line steps, which means it has obvious advantage in the design of fast response switching converters and LED drivers [22-27]. However, the switch frequency will undergo some changes accordingly with the input and output voltage, which complicates electromagnetic interference shielding in electronics equipments. In addition, several LED dimming techniques have been used to provide higher efficiency [4], higher dimming linearity [15], higher dimming ratio [11, 13, 22] and faster dimming speed [14]. Nowadays, LED drivers tend to integrate different kinds of dimming techniques to increase the flexibility of the system design [12]. In this paper, an adaptive off-time method is adopted to the synchronous buck LED driver to both suppress the variation of switching frequency and achieve the fast response without external loop compensation. The peak current is detected by sensing the voltage drop on the high-side power switch, which avoids both the power losses and application cost caused by the sense resistor and suppresses the bad influence on sampling accuracy caused by process drift and temperature variety. Furthermore, the integrated full-range analogue and fast pulse-width modulation (PWM) dimming techniques are easy to implement and featured with a high linearity in wide range and excellent contrast ratios. The rest of this paper is organised as follows. In Section 2, the system architecture with the proposed structure is described. In Section 3, the principle scheme and design of the circuits are presented. The experimental results are discussed in Section 4. Finally, the conclusion is given in Section 5. 2 Architecture and principle of the adaptive off-time LED driver On the basis of the topology of synchronous buck DC–DC converter, the function block diagram of the proposed LED driver with adaptive off-time control is shown in Fig. 1. M1 and M2 are internal integrated power switches, which are helpful to improve the integration and reduce the area and cost of application of circuit. The duty cycle signal VPWM is generated by the analogue and feedback control block which consist of two major circuits, one is the adaptive off-time generation circuit and the other is the peak current detecting circuit. At the beginning of a switching period, M1 is turned on to increase the inductor current. When the peak current is detected, the output of the peak current detecting circuit, VT, triggers the signal of the off-time to turn off M1. The on-time duration is decided. At this particular time, M2 will be turned on to discharge the inductor current. Once the off-time is terminated, M1 will be turned on again. The periodic switching waveforms of constant peak current are obtained with such cycle. Since the peak value of the inductor current is fixed, the average current flowing through the LED keeps constant. Fig. 1Open in figure viewerPowerPoint System function block of the proposed LED driver In addition, PWM and analogue dimming techniques are integrated in the proposed driver. The digital PWM dimming can be realised from the EN pin. The PWM signal VEN produces two control signals VEN1 and VEN2, VEN1 is used as the whole chip enable signal and VEN2 is used for PWM dimming logic control signal. When VEN2 is high, peak current detecting circuit operates normally; when VEN2 is low, the power transistor M1 is turned off rapidly. To avoid the false shutdown of the whole chip caused by the PWM dimming process, a delay time is added to VEN2 on the falling edge of the VEN2. Besides, analogue dimming can be accomplished by changing the input voltage on VADJ pin or adjusting the value of the dimming resistor RADJ. The typical control timing diagram of the PWM and analogue dimming is shown in Fig. 2, and VDH is the driver signal of the high-side power switch M1. The front half part shows the PWM dimming, and the second half shows the analogue dimming by changing the VADJ voltage. Fig. 2Open in figure viewerPowerPoint Typical control timing diagram of the PWM and analogue dimming 3 Proposed circuits of the system 3.1 Peak current detecting circuit The proposed peak current detecting circuit is shown in Fig. 3, which is composed of four basic units: peak current detecting unit, analogue dimming unit, power stage and driver unit, and floating ground unit. The proposed circuit is used to realise the peak inductor current detection by sampling the current of the high-side power switch M1. Moreover, the power stage and driver unit is used to convert the duty cycle control signal VPWM into the power transistors' driver signal. The peak current detecting unit is provided to detect the inductor's peak current through sampling conduction voltage drop across the high-side power switch M1. Moreover, the analogue dimming unit is used for setting the comparator's threshold voltage by adjusting the reference current, IREF. Fig. 3Open in figure viewerPowerPoint Peak current detecting circuit The maximum input voltage of the proposed driver is defined as 40 V, therefore, in this circuit, the power switches M1 and M2 as well as other high-voltage isolation transistors are 40 V double-diffused MOSFET (DMOS) devices, which can be distinguished by the double line in their drain. While the rest of the transistors are 5 V metal oxide semiconductor (MOS) devices. As the gate–source breakdown voltage of the DMOS is well below its drain–source breakdown voltage, the gate–source operating voltage of a 40 V DMOS in the adopted process is 5 V. To be compatible with low-voltage logic level, a level shifter is required to convert VPWM into the driver signal, which uses the structure shown in the literature [28]. The logic level in front of the level shifter is from 0 to 5 V and behind the level shifter is from (VIN−5 V) to VIN. And (VIN−5 V) is represented by VFGND which is preset by the floating ground unit. To ensure the driving capability of the M1 gate, VFGND must have sufficient dropping current capacity. As shown in Fig. 3, VFGND can be expressed as (1) (2)where VREF2 is the reference voltage and VTH13 is the threshold voltage of M13. The peak current detecting unit senses the peak inductor current by comparing the conduction voltage drop across the high-side power switch M1 with the comparator's threshold voltage, VITH, which is indirectly determined by the voltage drop on M3. To cancel the offset caused by the temperature change and process drift, M1 is well matched with M3. M4 is turned on to detect the inductor current by the comparator, COMP, when M1 is turned on. A delay time, TD, is generated by the delay cell between the signal VLS and signal VLSD to eliminate the switching noise to the comparator. When the inductor current reaches the peak value, the output signal of comparator, VT, goes high, M1 is turned off and the off-time starts. Meanwhile, M4 is turned off and M5 is turned on, the negative terminal of COMP is pulled to VIN. After the off-time is terminated, the comparator outputs low signal and waits for the next peak current detection cycle. The specific time sequence of the control signals is shown in Fig. 4. Fig. 4Open in figure viewerPowerPoint Specific time sequence of the control signal As discussed above, once the inductor peak current is detected, the inductor current, IL-peak can be written as (3)where IREF is the reference current which is produced by the analogue dimming unit, are the on-resistances of M1 and M3. For they operate in the deep triode region and their on-resistance can be approximated as (4)Hence, IL-peak can be rewritten as (5) (6)By (5) and (6), it is obvious that the peak inductor current is determined by IREF and the ratio of M1 and M3, and the offset caused by the temperature change and process drift is effectively eliminated. IREF can be programmed by changing the input voltage on VADJ pin or adjusting the value of the dimming resistor RADJ, which is realised by the analogue dimming unit as shown in Fig. 3. When the VADJ pin is floating, IREF can be expressed as (7)R1 and R2 are the same types of internal resistances, which are designed to be equal and well matched. RADJ is an external resistor and maintains zero temperature coefficient and high precision. Hence, IL-peak can be rewritten as (8)When the pin of VADJ inputs a voltage, IL-peak can be rewritten as (9)The proposed comparator is shown in Fig. 5a, which consists of four stages, the first and the second stages are general differential structures, the third stage is a fully differential fold-cascode structure and the fourth stage is a level shifter. The first three input stages of comparator adopt resistances as load, which not only reduce the input offset and kickback noise, but also avoid the increasing of the circuit complexity brought by the common mode feedback of current mirror load [29]. The level shifter is used to convert the logic level under high-voltage VIN into the logic level under low-voltage VDD. M24 is used to clamp the high voltage of VX. M5, M9, M13 and M22 are used as both enable switches and high-voltage isolation devices. Fig. 5Open in figure viewerPowerPoint Peak current comparator circuit a Schematic diagram of the peak current comparator b Alternative circuit of the comparator's polarity In this proposed comparator circuit, all the transistors are well matched in layout and biased in the saturation region to make the comparator more vigorous against mismatch and process variations. IBIAS mainly determines the bias current of the whole circuit and VEN1 is a enable signal. When VEN1 is low, the comparator is off and the current source transistors are switched off, and there is no current path from the supply to ground. The threshold voltage VITH seen by the peak current comparator is affected by the comparator's input offset voltage, which causes an error in the calculation of IL-peak. To eliminate the input offset voltage, the design idea of chopper comparator is introduced into the peak current comparator. As shown in Fig. 5b, three alternative switches, S1, S2 and S3, are added to the input and output of the comparator. Hence, the polarity of the comparator inputs is swapped every switching cycle, which guarantees the actual IL-peak to alternate between two peak values. In addition, the d-flip-flop is used to generate the control signal of switches, and the sequential relationship between VT and VS is shown in Fig. 5b. 3.2 Adaptive off-time generation circuit The major drawback of COFT control is that the switching frequency changes with the duty cycle. The proposed adaptive off-time control can eliminate this change. For the buck DC–DC converter it holds (10) (10)where TSW is the switching period, D is the duty cycle and TOFF is the off-time of the switching period. According to (14), it can be concluded that the converter can maintain operating at a fixed frequency as long as TOFF is inversely proportional to the VIN and inversely proportional to (VIN–VOUT). To achieve the required off-time as discussed above, an adaptive off-time generation circuit is proposed in this paper as shown in Fig. 6. The off-time is triggered by the pulse signal VT. When VT goes high, C1 is discharged by M16. When VT goes low, C1 is charged by I5. Once VTOFF is up to VTH, the output of SR latch turns from high to low and the next peak current detection cycle starts. Fig. 6Open in figure viewerPowerPoint Adaptive off-time generation circuit In Fig. 6, divider resistance networks are used for the input and output voltage feedbacks, and they hold the same divider proportion, k2. The conversion relationship can be expressed as I1 = VOUTS/R3 and I2 = VINS/R6. Current mirrors M1–M8 and resistance R7 are used for setting the value of the comparator threshold voltage VTH. The theoretical derivation is shown as follows (11) (12)Supposing R3 = R6, then (13) (14)In this proposed circuit, R8 is equal to R6. M14 and M15 are designed with same ratio of W/L and with a longer length to weaken the impact on drain current caused by the effect of channel length modulation. Therefore it is easy to obtain that I5 is approximately equal to I2. Hence, the off-time, TOFF, can be expressed as (15)According to the above analysis, the desired fixed off-time is obtained, which is inversely proportional to the VIN and proportional to the (VIN–VOUT). Hence, the switching period TSW and switching frequency fSW of the driver are shown as below, respectively (16) (17)Therefore the steady-state switching frequency fSW, which is independent of the input voltage VIN and output voltage VOUT, can be easily evaluated by the passive components R7 and C1. 3.3 PWM dimming circuit PWM dimming can be achieved by a PWM input signal from the EN pin. Fig. 7a shows the PWM dimming circuit. The PWM signal VEN is processed to generate two internal control signals VEN1 and VEN2. VEN1 is used as the whole chip enable signal, and VEN2 is used as the PWM dimming logic signal. They can be distinguished by setting a delay time at the edge of low logic, which is defined as TD1, shown in Fig. 7b. When VEN keeps low, longer than TD1, it is recognised as a shutdown signal and VEN1 turns low to shutdown the whole chip. When VEN keeps low, shorter than TD1, it is considered as the PWM dimming logic signal and VEN2 goes low to turn off the high-side power switch M1 as shown in Fig. 6. Fig. 7Open in figure viewerPowerPoint PWM dimming a PWM dimming circuit b Dimming control waveforms As shown in Fig. 7a, when VEN turns high, capacitor C1 is discharged by M2, VN drops below the positive threshold of the Schmitt trigger to make VEN1 and VEN2 turn high quickly. When VEN turns low, the drain current of M1 starts to charge C1. Voltage VN is used to compare with the positive threshold of the Schmitt trigger, VT+. Once VN reaches VT+, the Schmitt trigger's output VEN1 goes low, which turns M3 on and makes VEN2 stay low. The delay time, TD1, is determined by the charge time of C1. As discussed above, VEN2 is used as the PWM dimming logic signal to directly turn on or turn off the high-side power switch, and the delay time between VEN2 and VEN is almost negligible. Hence, fast PWM dimming function can be achieved from EN pin. 4 Experimental results and discussions The proposed LED driver was implemented in 0.35 μm 40 V BCD process and the microphotograph of chip is shown in Fig. 8. Except for the functional blocks given in Fig. 2, the chip also integrates the proportional to absolute temperature (PTAT) current generator, bandgap reference, over-voltage protection, under-voltage protection circuits and so on. The analogue and feedback control circuit, driver circuit and power switch MOS are marked with black boxes in the layout. The on-resistances of high-side and low-side power switches are 100 and 60 mΩ, respectively. The switching frequency is designed at 500 kHz. The experimental results confirm that the LED driver can operate within 6–40 V input voltage, and can drive 1–10 output series connected LEDs. Fig. 8Open in figure viewerPowerPoint Chip microphotograph As discussed above, analogue dimming can be achieved by adjusting the voltage of VADJ pin or the value of RADJ. Fig. 9a gives the analogue dimming process with the voltage of VADJ. From Fig. 9a, it can be seen that when the voltage of VADJ linearly increases from 0 to 1.25 V, the average value of the inductor current also linearly increases from 0 to 3 A. Figs. 9b and c show the 1 and 2 A analogue dimming waveforms, from which it can be seen that the switching frequency is maintained at 500 kHz. Figs. 9d and e show the process of PWM dimming which is achieved by a 20 kHz square wave signal from VEN pin. From Figs. 9d and e, it can be seen that the inductor current delay times from VEN rising and falling edges are almost negligible. The settling time at the VEN rising and falling edges are <3.5 and 1.6 μs, respectively, which only depend on the inductor current rising and falling rates. Fig. 9Open in figure viewerPowerPoint Dimming process a Analogue dimming process with VADJ b Analogue dimming process with VADJ (ILED = 2 A) c Analogue dimming process with VADJ (ILED = 1 A) d Rising edge of PWM dimming e Falling edge of PWM dimming Fig. 10 displays the proposed circuit efficiency curves, respectively, in the case of 1 and 2 A LED current with 11–40 V input voltage range. The system efficiency higher than 87% at 2 A LED current, and the peak efficiency up to 95% at 1 A LED current is obtained. The relationship between switching frequency and VIN is given in Fig. 11. Although the input voltage changes from 12 to 40 V, the switching frequency variation quantity is <10 kHz. Fig. 10Open in figure viewerPowerPoint Efficiency against input voltage Fig. 11Open in figure viewerPowerPoint Switching frequency against input voltage Table 1 summarises the main performances of the proposed synchronous buck current regulator for LED driving applications in comparison with the state of the art [6, 26, 27]. The proposed LED driver provides higher output current with wider input and output voltage ranges while operating at a constant switching frequency. The proposed LED driver loop effectively reduces the settling time of the LED current compared with previous works. In addition, the integrated analogue and fast PWM dimming techniques in proposed LED driver are easy to implement and featured with a high linearity in wide range and excellent contrast ratios. Table 1. Proposed regulator performances compared with previous works 2013 [6] 2010 [26] 2014 [27] This work technology 0.35 μm HV CMOS 0.35 μm HV CMOS 0.5 μm HV CMOS 0.35 μm 40 V BCD input voltage range, V 10–40 8–40 11–20 6–40 maximum number of LEDs 10 8 4 10 maximum LED current, A 0.5 1.5 0.1 2.0 switching frequency, kHz various or constant ∼1000 various ∼188 various 50–200 various 500 constant inductor, μH 10–39 33 100–1000 22 peak efficiency, % 92.5 94.3 91.0 95 settling time, μs 8.5 120 50 3.5 dimming method PWM PWM N/A analogue/PWM 5 Conclusion A high-efficiency dimmable LED driver with adaptive off-time control from wide input voltage range is proposed, designed, built and experimentally validated with an IC prototype from 0.35 μm 40 V BCD process technology. With the adaptive off-time control, the driver can operate properly at 500 kHz fixed switching frequency which is not influenced by the input and the output voltages. Furthermore, both the full-range analogue dimming and fast PWM dimming options are easy to implement and provide high linearity in wide dimming range. The proposed driver not only needs no external loop compensation, but also obtains excellent transient response speed and shorter settling time for fast PWM dimming. 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