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Low Power Dynamic Buffer Circuits

2012; Volume: 3; Issue: 5 Linguagem: Inglês

10.5121/vlsic.2012.3505

0976-1357

Amit Kumar Pandey,

Parallel Computing and Optimization Techniques

In this paper we propose two buffer circuits for footed domino logic circuit.It minimizes redundant switching at the output node.These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption.Simulation is done using 0.18µm CMOS technology.We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply.Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.