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Dynamic Testing for Deadlocks via Constraints

2016; IEEE Computer Society; Volume: 42; Issue: 9 Linguagem: Inglês

10.1109/tse.2016.2537335

2326-3881

Yan Cai, Qiong Lu,

VLSI and Analog Circuit Testing

Existing deadlock detectors are either not scalable or may report false positives when suggesting cycles as potential deadlocks. Additionally, they may not effectively trigger deadlocks and handle false positives. We propose a technique called ConLock + , which firstly analyzes each cycle and its corresponding execution to identify a set of scheduling constraints that are necessary conditions to trigger the corresponding deadlock. The ConLock + technique then performs a second run to enforce the set of constraints, which will trigger a deadlock if the cycle is a real one. Or if not, ConLock + reports a steering failure for that cycle and also identifies other similar cycles which would also produce steering failures. For each confirmed deadlock, ConLock + performs a static analysis to identify conflicting memory access that would also contribute to the occurrence of the deadlock. This analysis is helpful to enable developers to understand and fix deadlocks. ConLock + has been validated on a suite of real-world programs with 16 real deadlocks. The results show that across all 811 cycles, ConLock + confirmed all of the 16 deadlocks with a probability of ≥80 percent. For the remaining cycles, ConLock + reported steering failures and also identified that five deadlocks also involved conflicting memory accesses.