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A New Hybrid 16-Bit*16-Bit Multiplier Architecture by m:2 and m:3 Compressors

2016; Volume: 6; Issue: 2 Linguagem: Inglês

10.18178/ijiee.2016.6.2.599

2010-3719

Shima Mehrabi, Reza Faghih Mirzaee, Sharareh Zamanzadeh, Amirhossein Jamalian,

Interconnection Networks and Systems

Compressors are mostly used in multipliers to reduce partial products in a parallel manner.Firstly, this paper draw a comparison between the conventional m:2 and m:3 compressors.Secondly, a new hybrid 16-bit16-bit multiplier is proposed in this paper with the aim of taking benefits from both kinds of compressors.The new design decreases the amount of carry signals by employing m:3 compressors in the first stage.It also accelerates reducing partial products by using m:2 compressors in the following stages.The second and third phases of multiplication are considered together in this paper.The synthesizable structural VHDL code is used to simulate and implement different architectures.Our investigations demonstrate that the new multiplier is the fastest one with reasonable power and area dissipations.