High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering
2016; Institution of Engineering and Technology; Volume: 11; Issue: 6 Linguagem: Inglês
10.1049/mnl.2015.0526
ISSN1750-0443
AutoresKaushal Nigam, P. N. Kondekar, Dheeraj Sharma,
Tópico(s)Integrated Circuits and Semiconductor Failure Analysis
ResumoMicro & Nano LettersVolume 11, Issue 6 p. 319-322 ArticleFree Access High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering Kaushal Nigam, Corresponding Author Kaushal Nigam connecttokaushal@gmail.com Nanoscale Device, Circuit and System Design Laboratory, Electronics and Communication Engineering Discipline, Indian Institute of Information Technology, Jabalpur, 482005 IndiaSearch for more papers by this authorPravin Kondekar, Pravin Kondekar Nanoscale Device, Circuit and System Design Laboratory, Electronics and Communication Engineering Discipline, Indian Institute of Information Technology, Jabalpur, 482005 IndiaSearch for more papers by this authorDheeraj Sharma, Dheeraj Sharma Nanoscale Device, Circuit and System Design Laboratory, Electronics and Communication Engineering Discipline, Indian Institute of Information Technology, Jabalpur, 482005 IndiaSearch for more papers by this author Kaushal Nigam, Corresponding Author Kaushal Nigam connecttokaushal@gmail.com Nanoscale Device, Circuit and System Design Laboratory, Electronics and Communication Engineering Discipline, Indian Institute of Information Technology, Jabalpur, 482005 IndiaSearch for more papers by this authorPravin Kondekar, Pravin Kondekar Nanoscale Device, Circuit and System Design Laboratory, Electronics and Communication Engineering Discipline, Indian Institute of Information Technology, Jabalpur, 482005 IndiaSearch for more papers by this authorDheeraj Sharma, Dheeraj Sharma Nanoscale Device, Circuit and System Design Laboratory, Electronics and Communication Engineering Discipline, Indian Institute of Information Technology, Jabalpur, 482005 IndiaSearch for more papers by this author First published: 01 June 2016 https://doi.org/10.1049/mnl.2015.0526Citations: 13AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract A novel dual metal gate doping-less vertical tunnel field effect transistor (D-VTFET) on silicon body, using work function engineering is proposed. The proposed structure does not required impurity doping for formation of the drain and the source regions. In this concern, source and drain regions are formed by selecting appropriate work-function of metal electrode. The source and drain regions are not formed by conventional ways of ion implantation or diffusion. Hence, proposed structure is immune greatly to the process variation, issues of doping control and random dopant fluctuations which are serious problems in ultrathin silicon devices. For further improvement in ON state current and analogue/RF figures of merit dual work function of single gate material is considered. The electrical characteristics of the proposed device with the D-VTFET are simulated and compared. 1 Introduction In the near future, tunnel field effect transistor can be considered as a potential candidates to take over classical bulk MOSFETs due to its lower subthreshold swing, lower leakage current in off state and more immunity towards short-channel effects [[1]-[3]]. However, in case of Si TFET smaller value of ON-state current due to poor band to band tunnelling and random variability because of random dopant fluctuation are two major problems. To enhance the ON-state current, TFETs are being realised using hetero material, gate with high-k dielectrics material and gate all around TFETs [[4]-[7]]. Apart from these issues, by the existence of doped region, generates the requirement of complex thermal budget for ion implantation and expensive thermal annealing methods. To overcome the above mentioned problem, we investigated an approach to designate a doping-less vertical tunnel field effect transistor (D-VTFET) with dual metal gate and high-k material. This proposed device is based on work function engineering, in which there is no need of doping on silicon. For this, the p-type and the n-type regions for source and drain are formed on undoped silicon body by selecting the appropriate work functions of metal electrodes. Further, the dual materials are chosen to bring trade of between the ON-state current (ION) and the OFF-state current (IOFF) of the proposed structure. Whereas, use of high-k dielectric provides the better coupling between the gate and the tunnel junction, results in improved performance of D-VTFET. Thus, the important merits of the proposed device are absence of doped region which avoid the thermal budget due to expensive annealing equipment and improved performance due to presence of dual work function of single gate material. However, the physical realisation of dual work function on a gate electrode is a challenging task. The advancement in nanolithography and taking molybdenum as a gate material offers integration of dual work function on a gate electrode using high dose nitrogen implantation [[8], [9]]. The Letter is followed as: Section 2 illustrates device electrostatics. Section 3 demonstrates the DC characteristics and analogue/RF performance. Finally, conclusion is summarised in Section 4. 2 Device electrostatics Illustration of cross-sectional view of (i) Conventional VTFET (ii) D-VTFET and (iii) the dual metal gate doping-less VTFET is shown in Fig. 1. The basic parameters have been used for the conventional device [[4], [10]]: channel region doping (Nc) = 1 × 1017 cm−3, source region doping (Ns) = 1 × 1020 cm−3, drain region doping (Nd) = 5 × 1018 cm−3, gate length (Lg) = 50 nm, silicon body thickness (TSi) = 10 nm, gate dielectric thickness (Tox) = 3 nm, and gate work function (ϕm) = 4.5 eV. For the dual metal gate the work function of tunnelling gate (M1) and auxiliary gate (M2) are considered as 4.0 and 4.6 eV respectively. Whereas, tunnelling gate (M1) length is 20 nm and auxiliary gate (M2) is 30 nm. The simulation parameters for D-VTFET are identical as mentioned for conventional VTFET except the formation of p-type source and n-type drain region over the intrinsic silicon film is performed by using charge plasma concept. For this, the charge plasma based approach is depend upon conditions: (i) under the thermal equilibrium condition, the work function of metal source electrode (Platnum work-function ) must be greater than that of silicon for creating the p-type region and for the drain metal electrode (Hafnium work function (ϕm) = 3.9 eV) the work function must be less than that of silicon for creating the n-type region [[10]-[14]] i.e. ϕmS > χSi + (EG/2q) and ϕmD < χSi + (EG/2q). Here, EG is band gap of bulk silicon; χSi is the electron affinity of bulk silicon, and q is the elementary charge. Apart from this, Lgap, D = 15 nm and Lgap, S = 3 nm as shown in Fig. 1b. Further, in order to cease the possibility of silicide formation, we introduced a 0.5 nm thick film between the silicon film and metal electrode over the drain and source regions. The alternative way is also possible to reduce the silicide formation by the use of bias during the metal sputtering [[15]]. We have introduced a 3.0 nm oxide (SiO2) between the source/drain metal electrodes and thin film silicon in order to get carriers concentration similar to that of conventional VTFET. The thickness of silicon body must be less than the debye length (), here, ɛSi is the dielectric constant of silicon, vt is thermal voltage, q is the elementary charge, and ni is the carrier concentration of the thin film silicon. If the silicon film grows epitaxially, the simulation result remains same even if the silicon thin film carrier concentration is higher than ni. The technology computer aided design simulation has been performed by using 2D-ATLAS device simulator [[16]]. Non-local BTBT model is included to account for tunnelling current, which depends on the band structure along the cross section taken through the device. Further, Schenks trap assisted tunnelling model is used to account electron tunnelling by the trap states and Quantum confinement model is used to account for the effect of quantum confinement and interface trap on BTBT [[16]]. The Wentzel–Kramer–Brillouin method is invoked for the numerical solution. Fig. 1Open in figure viewerPowerPoint Schematic view of a Conventional VTFET b Doping-less VTFET c Dual metal gate doping-less VTFET 3 Results and discussions This section illustrates the behaviour of the proposed device D-VTEFET in terms of DC characteristic and analogue/RF performance for ultra-low power applications. For this, the comparisons of carrier concentration and energy band diagram are considered for conventional and D-VTFET. Further, the improvement in performance of D-VTEFET is obtained by using dual work function of gate electrode. 3.1 DC characteristics Fig. 2a depicts the electron and hole concentration under thermal equilibrium and ON-state conditions of the D-VTFET. It can be observed that in thermal equilibrium condition the induced electron and hole concentrations are 1019 cm−3 at drain and source regions, respectively due to presence of lower work function (3.9 eV) at drain region and higher work function (5.93 eV) at source region. Energy band diagram of ON-state and OFF-state conditions is shown in Fig. 2b for the D-VTFET. We can see from the same figures, at ON-state condition, energy of valence band of the source region is aligned with the energy of conduction band of the channel region. So that the width of tunnelling barrier is reduced significantly, which drastically enhances the tunnelling probability. Fig. 2c illustrates the energy band diagram in the ON-state condition along the channel direction at 1 nm away from Si/SiO2 interface and centre of the device. Further from the figure, we can observe at the centre of the device that the tunnelling barrier width is higher than that at interface of Si/SiO2, the varying tunnelling barrier width is due to the non-uniformly induce hole and electron concentration at the source and the drain side regions of D-VTFET as depicted in Fig. 2d. Fig. 2Open in figure viewerPowerPoint Schematic view of a Electron and Hole carrier concentrations of the D-VTFET under the thermal equilibrium and ON-state condition at 1 nm away from the Si/SiO2 interface b Energy band in OFF-state (VGS = 0 V, VDS = 1.0 V) and ON-state (VGS = 1.0 V, VDS = 1.0 V) at 1 nm away from the Si/SiO2 interface c Energy band diagram in ON-state (VGS = VDS = 1.0 V) for the doping-less VTFET along the channel direction at 1 nm away from Si/SiO2 interface and centre of the device d Electron and hole concentrations in source and drain regions along the body thickness of D-VTFET Fig. 3a depicts electron and hole concentration variation along the channel direction of the conventional VTFET (doted line) and D-VTFET (solid line) under the thermal equilibrium (VDS = 0, VGS = 0). From this figure, we analysed that the profile of electron and hole concentration of the proposed device structure are nearly same as that of conventional VTFET. The reason is that when the high work-function metal electrode brought in the contact of intrinsic silicon film causes accumulation of holes near the metal semiconductor interface. Whereas, the presence of low work-function metal electrode over the intrinsic silicon film causes accumulation of electron near the metal-semiconductor interface. Hence, the D-VTFET device is identical to the conventional VTFET. For this, Fig. 3b represents the diagram of energy band along the channel direction for the conventional VTFET (doted line) and doping-less VTFET (solid line) under the thermal equilibrium. Under this circumstances, there is an existence of potential barrier in the channel of D-VTFET (solid-line) owing to work-function difference between the silicon and the gate material similar to conventional VTFET (doted line), it does not allow the tunnelling current. Fig. 3c shows the profile of electron and hole concentration in OFF-state (VDS = 0, VGS = 0). It can be observed that lesser the electron and higher the hole concentration in the channel of D-VTFET is responsible for OFF-state current which shows the nearly similar behaviour to that of conventional VTFET. For both devices, the probability of passing electron is very less because the tunnelling width is very large (>10 nm) between source and channel. Hence, the tunnelling probability is reduced as depicts in Fig. 3d in OFF-state condition. Further to this, Fig. 3e shows the profile of electron and hole concentration in ON-state (VDS = 1.0 V, VGS = 1.0 V). It can be observed that higher the electron and lesser the hole concentration in the channel of D-VTFET is responsible for ON-state current which resemble the conventional VTFET. Fig. 3f shows the narrow barrier width between channel and source region by applying the positive gate voltage for both the devices in ON-state condition which allows the tunnelling current from drain to source due to reduction of tunnelling width below the 10 nm. Fig. 3Open in figure viewerPowerPoint Shows the carriers concentration and energy band diagram of conventional VTFET and Doping-less VTFET a Carrier concentration at thermal equilibrium condition b Energy band diagram under thermal equilibrium condition c Carrier concentration at OFF state condition d Band diagram under OFF state condition e Carrier concentration at ON state condition f Band diagram under ON state condition Transfer characteristics of the D-VTFET and VTFET are represented in Fig. 4a for VDS = 1 V. From this figure, it can be observed that the OFF current is as low as and the ON current is for D-VTFET, which is much alike to that of the conventional VTFET. The thickness of spacer is an important parameter of the proposed device. It measures the closeness of the gate field to the tunnelling path on the source side. From Fig. 4b, it is observed that the ON-state current decreases as Lgap,S increases from 3 to 15 nm due to reduction in abruptness of the source channel junction gradient. Thus, the selection of Lgap,S is responsible for tunnelling probability. The output characteristics of the D-VTFET is as illustrated in Fig. 4c. From the same figure, it can be detected that there is no outstanding change in tunnelling width with change in VDS under saturation region, hence, the current remains same in this region. Fig. 4Open in figure viewerPowerPoint Transfer characteristics of the D-VTFET and VTFET a IDS against VGS characteristics of the D-VTFET and conventional VTFET b Drain current of the D-VTFET with the spacer thickness at the source side c Output characteristic of D-VTFET Further, increment in the drain current have been spotted for increment in gate voltage (VGS) due to more band bending. From the same transfer characteristics of D-VTFET, we can detect that, the ON state current of tunnel field effect transistor (TFET) are subjects of grave concern. For this, we consider the novel dual metal gate (DMG) D-VTFET results in further improvement in ON state current. In this context, the ON state current and analogue/RF figures of merit (FOMs) are analysed by dual work function of single gate material. 3.2 Analogue/RF performance In this section, the improvement in device performance of D-VTEFET is obtained by using dual work function of gate electrode. Further, the Analogue/RF FOMs are extracted on simulating small signal frequency at 1 MHz ac device. Variation of IDS with respect to VGS of D-VFET and DMG D-VTFET is shown in Fig. 5a. It is observed that ION and SS improves with DMG D-VTFET due to presence of lower work function of tunnelling gate in case of DMG D-VTFET. Hence, the higher ION/IOFF ratio and better switching performance obtained in case of DMG D-VTFET. The important parameter for analogue/RF performance is transconductance can be defined as gm = δIDS/δVGS i.e. the gain of the device and should be high enough for enhancing RF performances. Fig. 5b illustrates the comparison for transconductance of D-VTFET and DMG D-VTFET as a function of gate bias. Important parameter gm increases with VGS, which decides the gain, due to enhancement in current driving capability of the respective device. Fig. 5Open in figure viewerPowerPoint Variation of IDS with respect to VGS of D-VFET and DMG D-VTFET a Transfer characteristics of the DMG D-VTFET and D-VTFET b Transconductance (gm) with respect to gate voltage of the DMG D-VTFET and D-VTFET c Output conductance (gds) as a function of gate voltage of the DMG D-VTFET and D-VTFET From the same figure significant improvement is observed in gm of DM-DVTFET due to better ION by the presence of tunnelling gate with lower function. The output conductance at any applied gate bias is defined as gds = (δIDS)/(δVDS) volt/amp where VDS and IDS are the drain voltage and drain current, respectively. From Fig. 5c, it has been detected that output conductance increases with drain to source voltage due to reduction in channel barrier. However, the output conductance decreases at high VDS because rate of increment in tunnelling decreases. Further, it can be observed that gds of DMG D-VTFET is higher than D-VTFET due to accumulation of extra electrons in the channel region. The important parameter of RF analysis, frequency at which short circuit current gain of the device falls to unity i.e. fT and can be expressed as fT = gm/2π (Cgs + Cgd), here, Cgd is gate to drain capacitance, whereas, Cgs is the gate to source capacitance. The parameter fT depends on Cgd, Cgs and on the other important parameter gm as depicted in Fig. 5b. We can spot that gm increases with VGS due to injection of charge carriers from the source region and increment in band to band tunnelling. However, Figs. 6a and b shows that Cgd increase with gate bias voltage, due to reduction in channel to drain potential barrier or in other terms, by the formation of inversion layer from the drain region side towards source region end. It also causes the better coupling between the gate to drain terminal, which is responsible for increment in Cgd with respect to VGS whereas Cgs is decreased due to presence of potential barrier as the gate to source voltage increases. Fig. 7 illustrate the significant initial increment in fT in case of DMG D-VTFET due higher current driving capability, for higher value of VGS it falls due to combined effect of accelerated increment in Cgd, Cgs and limiting of gm due to mobility degradation. Fig. 6Open in figure viewerPowerPoint Gate to source and gate to drain capacitances with gate to source voltage (VGS) Fig. 7Open in figure viewerPowerPoint Cutoff frequency (fT) with respect to gate to source voltage (VGS) The other vital specification of RF performance is the gain bandwidth product (GBP), for a certain DC gain = 10, can be expressed as fA = gm/2π 10Cgd is shown in Fig. 8. The better performance of DM-DFET in terms of GBP and changes occurs with VGS due to same reasons as discussed for fT. Fig. 8Open in figure viewerPowerPoint GBP as a function of gate to source voltage (VGS) 4 Conclusion We have proposed a unique structure of doping-less vertical tunnel field effect transistor on an ultra-thin undoped silicon film using the work function engineering. This method is based on selecting the suitable work-function in the metal electrodes for the formation of p-type source and n-type drain regions. Our results elaborates, that the performance of the D-VTFET is much similar in characteristics to that of a corresponding doped VTFET. The proposed D-VTFET is immune from random doping fluctuations because it is not using diffusion or ion-implantation for realising of source and drain regions. Moreover, a dual material gate in D-VTFET is used to optimise the analogue/RF performance. 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