A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current
1995; Institute of Electrical and Electronics Engineers; Volume: 30; Issue: 11 Linguagem: Inglês
10.1109/4.475704
ISSN1558-173X
AutoresH. Yamauchi, T. Iwata, Akito Uno, Motoyuki Fukumoto, Tsutomu Fujita,
Tópico(s)Advancements in Semiconductor Devices and Circuit Design
ResumoA 16M self-refresh DRAM achieving less than 0.5 /spl mu/A per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a V/sub BB/ pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 /spl mu/A per megabyte. Furthermore, the addition of a gate-received V/sub BB/ detector (GRD) reduces dc retention current to less than 0.1 /spl mu/A per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery.
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