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An Area-Efficient High-Resolution Resistor-String DAC with Reverse Ordering Scheme for Active Matrix Flat-Panel Display Data Driver ICs

2016; Institute of Electrical and Electronics Engineers; Volume: 12; Issue: 8 Linguagem: Inglês

10.1109/jdt.2016.2526042

1558-9323

Hyeon‐Cheon Seol, Seong‐Kwan Hong, Oh‐Kyong Kwon,

Advanced Memory and Neural Computing

In this paper, we propose an area-efficient high-resolution resistor-string digital-to-analog converter (R-DAC) with a reverse ordering scheme for active matrix flat-panel display data driver ICs. The proposed R-DAC is implemented in a two-stage DAC along with a DAC-embedded amplifier. The reverse ordering scheme reduces the area of the proposed R-DAC, which occupies most of the area of the data driver IC. To verify the reverse ordering scheme, a 640-channel data driver IC with a 12-bit two-stage DAC was fabricated using a 0.18-μm CMOS process with 1.8 V and 18 V devices. The fabricated 12-bit two-stage DAC comprises a 10-bit R-DAC with the reverse ordering scheme and a 2-bit DAC-embedded amplifier. The proposed 10-bit R-DAC occupies only 50.1% of the area of a conventional 10-bit R-DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.25/-0.26 LSB and +0.54/-0.42 LSB, respectively. The measured inter-channel and inter-chip deviation of voltage outputs are 2.40 and 7.42 mV, respectively.