Design and implementation of HyperTransport cave interface
2008; China Aerospace Science and Industry Group; Linguagem: Inglês
ISSN
1000-7024
Autores Tópico(s)Engineering and Test Systems
ResumoBased on HyperTransport I/O link specification revision 3.00,a HyperTransport(HT) cave interface based on FPGA is designed and implemented.The 8-bit HT cave interface architecture is presented,including the physical layer,data link layer,transport layer.The adapter with full-duplex transceiver on three virtual channels,is designed to solve the alignment bit-matching problem between the internal bus of HT core and HT link,and to realize a packet processing element for the analysis of HT components.Atlantic interface is used to adapter users.FPGA-based HT cave interface had finished a joint test with AMD chipset,and the results shows that the access bandwidth is 1.6GB/s on HT link.
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