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A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

2016; Institute of Electrical and Electronics Engineers; Volume: 25; Issue: 1 Linguagem: Inglês

10.1109/tvlsi.2016.2567784

1557-9999

Mario Garrido, Miguel A. Sanchez, Marisa López‐Vallejo, Jesús Grajal,

Model Reduction and Neural Networks

This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.