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Memory Interfaces: Past, Present, and Future

2016; Institute of Electrical and Electronics Engineers; Volume: 8; Issue: 2 Linguagem: Inglês

10.1109/mssc.2016.2546659

1943-0590

Chulwoo Kim, Hyun-Woo Lee, Junyoung Song,

Parallel Computing and Optimization Techniques

Over the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known "memory wall" problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM?