Family of step‐up DC/DC converters with fast dynamic response for low power applications
2016; Institution of Engineering and Technology; Volume: 9; Issue: 14 Linguagem: Inglês
10.1049/iet-pel.2016.0029
ISSN1755-4543
AutoresMohsen Soltani, Ali Mostaan, Yam P. Siwakoti, Pooya Davari, Frede Blaabjerg,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoIET Power ElectronicsVolume 9, Issue 14 p. 2665-2673 Research ArticlesFree Access Family of step-up DC/DC converters with fast dynamic response for low power applications Mohsen Soltani, Corresponding Author Mohsen Soltani sms@et.aau.dk Department of Energy Technology, Aalborg University, 6710 Esbjerg, DenmarkSearch for more papers by this authorAli Mostaan, Ali Mostaan Iranian Central Oil Field Co., Tehran, IranSearch for more papers by this authorYam Prasad Siwakoti, Yam Prasad Siwakoti Department of Energy Technology, Aalborg University, 9220 Aalborg, DenmarkSearch for more papers by this authorPooya Davari, Pooya Davari Department of Energy Technology, Aalborg University, 9220 Aalborg, DenmarkSearch for more papers by this authorFrede Blaabjerg, Frede Blaabjerg Department of Energy Technology, Aalborg University, 9220 Aalborg, DenmarkSearch for more papers by this author Mohsen Soltani, Corresponding Author Mohsen Soltani sms@et.aau.dk Department of Energy Technology, Aalborg University, 6710 Esbjerg, DenmarkSearch for more papers by this authorAli Mostaan, Ali Mostaan Iranian Central Oil Field Co., Tehran, IranSearch for more papers by this authorYam Prasad Siwakoti, Yam Prasad Siwakoti Department of Energy Technology, Aalborg University, 9220 Aalborg, DenmarkSearch for more papers by this authorPooya Davari, Pooya Davari Department of Energy Technology, Aalborg University, 9220 Aalborg, DenmarkSearch for more papers by this authorFrede Blaabjerg, Frede Blaabjerg Department of Energy Technology, Aalborg University, 9220 Aalborg, DenmarkSearch for more papers by this author First published: 01 November 2016 https://doi.org/10.1049/iet-pel.2016.0029Citations: 17AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract This study presents a family of novel step-up DC/DC converters which do not have a right half plane zero in their transfer function resulting in faster dynamic behaviour of the converters under the load variation. In addition, the voltage stress on all the active switches and diodes is as low as the input voltage level. The basic topology of this converter has a voltage gain of up to two in steady state. The derivatives of the converter are realised by adding a switched capacitor voltage multiplier cell in order to increase the voltage gain further. The most salient feature of these converters is presence of only two switches in the basic converter and its derivatives. The dynamic performance of the proposed converter and its first derivative is analysed by small-signal model using the state-space averaging method. The theoretical model is verified by experiments using GaN high-electron-mobility transistors with 1 MHz switching frequency. Nomenclature Variables are indicated by lowercase letters, e.g. vo, while their steady-state values are shown by capital letters, e.g. Vo. Variation of a signal, x, about its steady-state value, X, is indicated by , i.e. . 1 Introduction Dynamic response of DC/DC power converters is gaining more interest with the advent of low-voltage digital and portable power electronics applications [1]. Although most of studies have been dedicated to design of power converters with a fast dynamic performance, this issue has remained a challenging task when it comes to step-up power converters. Traditionally, step-up (boost) power converters suffer from a slow dynamic response due to the presence of a right-half plane zero (RHPZ) in their transfer function. With the current trend towards having more efficient and compact (high power density) power converters using wide bandgap semiconductor devices, designing a boost power converter with a fast transient response becomes a lot more cumbersome if the RHPZ is not effectively eliminated from its transfer function. The conventional boost converters can be utilised to increase and adjust the voltage level for such applications. However, their dynamic response is usually slow as they have an RHPZ in their control transfer function. In addition, the voltage stress on the switching devices needs to be low in order to use low Ron switches to reduce the losses. On the other hand, in conventional boost converters, the voltage stress on the power switch and the diode is as high as the output voltage, which requires a metal–oxide–semiconductor field-effect transistor with a high Ron that increases the power losses [2]. In addition, the capacitor current pulsates, resulting in the output voltage ripple to be large [3]. Therefore, the conventional boost converters are less suited to applications, where the output voltage ripple is one of the key demands. Several non-isolated step-up DC/DC converters are introduced in literature [4-12]. Although, the voltage gain is high, these converters represent at least one RHPZ. An RHPZ in the transfer function of the converter leads to slow dynamic response to load variations. It also decreases the closed-loop bandwidth of the converter [13]. For low power applications, KY converters have been introduced in [14-17]. In [14], a KY converter and its derivatives have been introduced such that no RHPZ is present in their control-to-output transfer function making their dynamic behaviour very fast. In addition, these converters always work in continuous conduction mode (CCM) similar to the synchronous buck converter. Therefore, a small inductor can be utilised in these converters that can lead to less occupied space that makes them suitable in compact devices. A drawback of these converters is that the number of the power switches increases correspondingly with the increase of the voltage gain. Consequently, the cost of the converter, which is highly affected by the power switches, increases to obtain higher voltage gain. In addition, the voltage stress on some switches and diodes is increased linearly with respect to the voltage gain, which also demands costly power switches. In [15-17], a family of KY buck–boost converter with positive and negative output voltage have been presented with four switches in its structure. In [18], a novel step-up DC/DC converter with no RHPZ has been introduced with only two switches in that converter and its derivative. A drawback of these topologies is that the input voltage and the load do not share the common ground that makes them inappropriate in many applications. An effective method to realise a compact DC/DC converter is to eliminate the inductor in converter structure [19, 20]. Switched capacitor converters are well developed during the last two decades and found in many applications [21]. However, the output voltage regulations in these converters are poor and the voltage gain is predetermined by the circuit structure [22]. Unlike the inductive switched mode pulse-width modulation (PWM) converters, the voltage gain in switched capacitors DC/DC converters is usually fixed according to their circuit configuration [23]. Therefore, the inductor-less switched capacitor DC/DC converters are more suitable for non-regulated applications, where maximum efficiency and minimum output voltage ripple is achieved in a fixed duty cycle [24]. By a combination of the switched capacitor cell with switched mode PWM DC/DC converter, high voltage gain in non-isolated converters can be realised while the voltage regulation can be obtained by adjusting the duty cycle [22, 25, 26]. Thus, a switched capacitor voltage multiplier cell [27, 28] is very effective for increasing the voltage gain in PWM non-isolated DC/DC converters. However, there is an RHPZ in these converters that have been introduced in [27, 28]. In this paper, a family of step-up DC/DC converters with a combination of the synchronous PWM DC/DC buck converter and switched capacitor cell is presented. The proposed converter has four advantages compared with the above topologies: (i) There is no RHPZ in its transfer function, which makes its dynamic response fast against the load variation. (ii) Unlike the inductor-less switched capacitor DC/DC converters, the output voltage regulation can be obtained by adjusting the duty cycle. (iii) Unlike the inductor-less switched capacitor DC/DC converter, the output voltage regulation can be obtained by adjusting the duty cycle without dependency on circuit parameters such as equivalent series resistance (ESR) of the capacitors and parasitic resistance of the switches. (iv) The voltage stress on all semiconductor devices is as low as the input voltage. Thus, low-voltage power switches are needed. Moreover, the voltage gain of this converter and its derivatives is identical with KY converter and its derivatives in [14]. However, the number of active switches in the proposed converter and all its derivatives are equal to two that are much lower than in the KY converter and its derivatives, i.e. 2N + 2, where N is the number of the derivative. This paper is organised as follows. The proposed converter is introduced in Section 2, where the steady-state and dynamic behaviour of the converter is analysed. In Section 3, the derivatives of the proposed converter and their steady-state and dynamic performance are introduced. Experimental results are provided in Section 4, where the performance of the proposed converter and its first derivative is verified by an experimental prototype using GaN transistors with 1 MHz switching frequency in 100 W nominal load and 25 V input voltage. 2 Proposed converter 2.1 Steady-state analysis The proposed converter is realised by adding switched capacitor cell into the synchronous buck converter as shown in Fig. 1. It consists of two switches that work complementary and work always in CCM. The duty cycles for S1 and S2 are D and 1 − D, respectively. Components C1, C2, D1 and D2 make a switched capacitor cell that is added to synchronous buck converter. There are two modes in every switching cycle that are shown in Figs. 1a and b. Fig. 1Open in figure viewerPowerPoint Structure of the proposed step-up converter and equivalent circuits in a switching cycle a Mode 1 b Mode 2 Fig. 1a shows that by turning S1 on, D1 will be forward biased while D2 will be reverse biased and C1 is charged with the input voltage. As a result, we have (1)Furthermore, S2 is off in mode 1 and its voltage is equal to the input voltage, i.e. . In mode 2, S1 turns off and S2 turns on, which results in C2 being in parallel with C1, and thus, the voltage across C2 will be equal to the voltage across C1, i.e. . Moreover, the voltage across the S1, D1 and D2 is as low as the input voltage value as shown in Figs. 1a and b, i.e. (2)Using Fig. 1a, the voltage across the inductor during mode 1 is given by (3)while Fig. 1b implies that the voltage across the inductor during mode 2 can be stated as (4)Using the voltage-second balance principle on the inductor, we have (5)Therefore (6)which infers the voltage gain to be (7)which is similar to the KY converter proposed in [14]. 2.2 Dynamic behaviour and small-signal modelling Following assumptions are considered in analysis of the converter: The dead time between switches is omitted. Voltage drop across all switches and diodes are negligible. All capacitors are large enough to keep their voltage constant in one switching cycle. Capacitors C1 and C2 are charged to the input voltage. The small-signal model of the proposed converter is obtained by using the state-space average modelling method. The state-space equation in mode 1 is as follows (8)while the state-space equation in mode 2 is given by (9)The average state-space model will be obtained by taking the weighted average on the state and input coefficients, where the weights are the duty cycles of each mode, i.e. (10)The averaged state space can be linearised around the quiescent point resulting in the following linear state-space equation (11)The resulting small-signal circuit for proposed converter is shown in Fig. 2. Fig. 2Open in figure viewerPowerPoint Small-signal model of the proposed converter From (11), the corresponding control input to the voltage output transfer function of the proposed converter is given as (12)which confirms that the proposed converter does not have a RHPZ. As a comparison, the control to output transfer function for conventional boost converter with neglecting the parasitic effects is [13] (13)which shows that the transfer function has a RHPZ at . Fig. 3 compares the dynamic behaviour of the proposed converter with that of the conventional boost converter with L = 1 mH. The voltage drop (undershoot) in the dynamic response of the conventional boost converter starts at 0.02 s as that the duty cycle is changed from D = 0.5 to D = 0.6. In contrast, the proposed converter does not have any voltage drop in its dynamic response and the output voltage is directly increased toward its final value. Fig. 3Open in figure viewerPowerPoint Dynamic response comparison of the proposed converter and conventional boost converter against the variation on duty cycle The presence of a RHPZ tends to decrease the bandwidth of the feedback loop, because during a transient the output initially changes in opposite direction [13]. In addition, the pole locations of the proposed converter transfer function are at (14)which implies a stable second-order response for all non-zero values of R, L and Co. 3 Derivatives of the proposed converter 3.1 Steady-state analysis From (7) it is clear that the maximum gain of the proposed converter is 2 that may not be sufficient in some applications. In order to increase the gain in this converter another switched capacitor cell can be added to it. The first derivative converter is shown in Fig. 4 that consists of two switches, two switched capacitor cells, one inductor and one output capacitor. In Fig. 4, it is obvious that unlike the KY converter the number of active switches remain unchanged. There are two modes in a switching cycle which are shown in Figs. 4a and b, respectively. Fig. 4Open in figure viewerPowerPoint First derivative of the proposed converter and equivalent circuits in a switching cycle a Mode 1 b Mode 2 In mode 1, S1 turns on and D1 and D3 conduct, while D2 and D4 are reverse biased. The capacitor C1 is charged to the input voltage. In mode 2, C2 is in parallel with C1. Therefore, the voltage across C1 and C2 is given by (15)From Fig. 4a the voltage across the C3 can be written as (16)Finally, from Fig. 4b, the voltage across the C4 is as follows (17)The voltage stress across the active switches is low and equal to the input voltage. The voltage stress across the diodes can be obtained using (15)–(17) as (18)Thus, the voltage across the inductor in mode 1 is given by (19)while the voltage across the inductor in mode 2 is (20)Using the voltage-second principle on the inductor, we have (21)and thus (22)which infers the voltage gain of (23)Furthermore, by neglecting all losses, the input power is equal to the output power. Thus, the relation between the average value of the input current and the output current in steady state is obtained as (24) 3.2 Dynamic behaviour and small-signal modelling Similar to the single-stage converter in the previous section, the state-space average modelling method can be used to obtain the dynamic behaviour and small-signal model of the double-stage converter. From Fig. 4a, the state-space equation in mode 1 is (25)while the state-space equation in mode 2 is given by (26)The average state-space model will be obtained by (27)The averaged state space can be linearised around the quiescent point resulting in the following linear state-space equation (28)From (28), the corresponding control input to voltage output transfer function of the proposed converter is given as (29)which confirms that the proposed converter does not have a RHPZ. 3.3 Nth derivative of the proposed converter To increase the voltage gain, more switched capacitor cells can be added to single-stage converter. Nth derivative of the proposed converter is shown in Fig. 5. This is realised by adding (N−1) switched capacitor cells to the single-stage converter. As shown in Fig. 5, there are two switches, 2N + 2 diodes, 2N + 3 capacitors and one inductor in Nth derivative of the proposed converter. With a similar method that was used in the previous sections, it can be shown that the voltage gain for Nth derivative of proposed converter is (30) Fig. 5Open in figure viewerPowerPoint Nth derivative of the proposed converter When S1 is turned on, the diodes with odd numbers (D1, D3, …, D2N+1) are in forward bias, while the diodes with even numbers (D2, D4, …, D2N+2) are in reverse bias. Also, when S2 is turned on, the diodes with odd number are turned off and the diodes with even number are turned on. The voltages across the capacitors with odd numbers are , , …, . The voltages on all capacitors with even numbers are equal to input voltage, i.e. . Consequently, the voltage stress on all diodes is low and equal to input voltage, . Also, the voltage stress on S1 and S2 are equal to the input voltage . In Table 1, the number of components between Nth derivative of the proposed converter are compared with the Nth derivative of KY converter in [14] and the inductor-less switched capacitor DC/DC converter in [19] with similar voltage gain. There are two switches in every derivative of the proposed converter. However, more diodes and capacitors are required in Nth derivative of the proposed converter compared with Nth derivative of the KY converter. From the voltage stress on the semiconductor devices view point, the voltage stress on all semiconductor devices is equal to input voltage in Nth derivative of the proposed converter, while the voltage stress on some switches and diodes in Nth KY converter are multiple times of the input voltage. Table 1. Comparison between N derivative of proposed converter and N derivative of KY converter in [14] and the converter in [19] Converter Switch Diode Capacitor Max. voltage stress proposed converter 2 2N + 2 2N + 3 Vin KY converter in [14] 2N + 2 N + 1 N + 2 converter in [19] 4N + 4 2N + 2 2N + 3 Vin If the voltage drop across the diodes is considered, it can be shown that the voltage across the capacitors with odd numbers is (31)Also, the voltage across capacitor with even numbers is (32)where VD is the voltage drop across the diodes. Using voltage-second balance principle on inductor, the output voltage can be obtained as (33)Thus, the output voltage is decreased when the voltage drop across diodes is considered. To obtain the desired gain, larger duty cycle or more switched capacitor cells are required compared with condition that the voltage drop across the diodes is neglected. Practically, the voltage drop across the diodes can be decreased considerably if diodes are replaced with Schottky diodes with smaller voltage drop or synchronous rectifier. 4 Design consideration The circuit parameters are determined according to characteristics shown in Table 2. Table 2. Design characteristics Characteristics Values input voltage 25 V output voltage (single stage, D = 0.75) 43.75 V output voltage (double stage, D = 0.75) 68.75 V current ripple across the inductor 2 A voltage ripple across each capacitor 0.5% of the nominal value switching frequency (f) 1 MHz 4.1 Inductor design Similar to synchronous buck converter, the proposed converter works in CCM even with higher inductor current ripple. Therefore, a small inductor is utilised in order to reduce the converter occupied space. Assume that the voltage across the capacitor is constant; the current ripple across the inductor in proposed converter can be calculated as (34)Therefore, the inductor value can be determined according to its defined maximum current ripple from (35)Similarly, the minimum value for inductor in first derivative of the proposed converter can be determined as (36)Using above equations, the minimum value of the inductor for the proposed converter and its first derivative is determined as 2.34 μH. Here, a 3.3 μH ferrite core 5 A inductor is selected for both topologies. 4.2 Output capacitor design Similar to conventional buck converter [29], the output capacitor voltage ripple can be approximated as (37)Therefore, the minimum value of the output capacitor can be calculated by (38)Thus, the minimum value of capacitors for proposed converter and its first derivative are calculated 1.1 and 0.73 μF, respectively. In experimental prototype, a 47 μF electrolyte capacitor with low ESR is selected for both converters. 4.3 Capacitors design for switched capacitor cell 4.3.1 Capacitor design for single-stage converter From Fig. 1a, it is clear that C2 discharges in mode 1 with inductor current. Neglecting the inductor current ripple, the inductor current is equal to the load current. Therefore, the voltage ripple across C2 in mode 1 is (39)As a result, the minimum value for C2 can be obtained as (40)Since capacitor C1 and C2 are in parallel in Mode 2, the voltage ripple across both capacitors are considered to be equal. Therefore (41)By selecting Io = 2.5 A, the minimum value for C1 and C2 is 15 μF. Thus, two 47 μF electrolyte capacitors are selected for both capacitors in order to reduce the voltage ripple further. Lower voltage ripple across capacitors can lead to lower current spike across the switches during the switching instance. 4.3.2 Capacitor design for first derivative of the converter From Fig. 4, it can be seen that C4 discharges with inductor current in mode 1. Therefore, the voltage ripple across C4 is (42)Thus, the minimum value for C4 can be obtained as (43)By using above equation, the minimum value for C4 is 15 μF. Using the ampere-second balance principle on C4 in mode 2, we have (44)that results in (45)Using Kirchhoff's current law (KCL) in Fig. 4, the current across C3 in mode 2 is (46)Using ampere-second balance principle on C3 in mode 1 gives (47)Therefore, the voltage ripple across C3 can be written as (48)From (48), the minimum value for C3 is determined as (49)With Io = 2.5 A and , the minimum value for C3 is 10 μF. Using KCL and ampere-second balance principle on C1 and C2, the voltage ripple across C1 and C2 is obtained as (50)and (51)With Io = 2.5 A and , the minimum values for C1 and C2 are 20 and 35 μF, respectively. In experimental prototype, 47 μF electrolyte capacitors are used for C1 to C4 in order to reduce the voltage ripple and current spike across the components during the switching instance. 4.4 Semiconductor selection The voltage stress on all semiconductor devices is low and equal to the input voltage. Therefore, switches with low drain–source voltage (VDS) are used. Consequently, GaN high-electron-mobility transistor (HEMT), which has a high switching ability and low drain–source voltage, are used in order to achieve acceptable power efficiency. Low-voltage, high-current diodes [V30DL50C-M3 (50 V, 30 A)] are selected for all experiments. 5 Experimental results A prototype of the single-stage and double-stage converter is built to verify the theoretical results. The components of the circuit are given in Table 3. Table 3. Circuit components Components Values S1 EPC2015 S2 EPC2023 L 3.3 μH, 5 A Single stage C1, C2, Co 47 μF, 50 V (conductive polymer aluminium solid electrolyte capacitor) D1, D2 V30DL50C-M3 (50 V, 30 A) Double stage C1–C4 47 μF, 50 V (conductive polymer aluminium solid electrolyte capacitor) Co 47 μF, 80 V (aluminium electrolyte capacitor) D1–D4 V30DL50C-M3 (50 V, 30 A) Other parameters are Vin = 25 V, D = 0.75, R = 20 Ω for single stage, and R = 50 Ω for double-stage converter. Photos of the prototypes of the single-stage and double-stage converters are shown in Fig. 6. The results consist of the open-loop and the closed-loop experiments for the single-stage converter and the open-loop experiment for the double-stage converter. The circuit parameters that are used in experimental results are similar to that of the simulation model. Switches put two capacitors in parallel, and thus, instantaneous high current flows in the diodes. Therefore, Si diodes with low voltage and high current are required in the proposed structure. GaN HEMT switches from EPC are used in prototypes. The switching frequency is in high-frequency band and is equal to 1 MHz with the input voltage of 25 V. The proposed converter and its derivative always work in CCM and never go into DCM even with a small inductor. Fig. 6Open in figure viewerPowerPoint Single and double-stage experimental prototype of the proposed converter The captured waveforms for a single-stage converter at D = 0.75 and Po = 100 W are shown in Fig. 7. The first traces in Fig. 7a show the gate–source voltage , drain–source voltage and drain–source voltage . It is clear that two switches work complementary, although a small dead time is used to avoid the short circuit across the input voltage. Also, the voltage stress across the switches showed to be low and equal to the input voltage. Fig. 7b shows the voltage across D1, D2, C1 and C2. The voltage stresses on both diodes are equal to the input voltage and the voltage across the capacitors is also equal to input voltage that is consistent with theory and simulation results. Fig. 7c shows the input voltage, input current, output voltage and output current. A small capacitor is put in parallel with the input voltage in order to smoothen the input current. Therefore, the input current is continuous and is about 3.9 A. The output voltage is about 44.6 V that is slightly lower than the theoretical results (45.5 V) because of the voltage drop on the diodes and other parasitic effects. Fig. 7Open in figure viewerPowerPoint Measured waveforms at D = 0.75, Vin = 26 V, Vo = 44.6 V, Po = 100 W, Efficiency = 93% a Ch1: , Ch2: , Ch3: b Ch1: , Ch2: , Ch3: , Ch4: c Ch1: Vin, Ch2: Iin, Ch3: Vo, Ch4: Io Fig. 8a shows the dynamic behaviour of the single-stage converter under open-loop condition when the duty cycle is changed from 0.5 to 0.78. The converter has a very fast response and there is no undershoot in output voltage waveform when the duty cycle is changed, i.e. there is no RHPZ in the proposed converter. The frequency response of the converter from the control input to the output voltage is obtained using a frequency analyser. Fig. 8b shows the gain and the phase of the experimental circuit that complies with the theoretical transfer function model 13. Fig. 8Open in figure viewerPowerPoint Time and frequency response of the converter a Measured open-loop response when duty cycle changed from 0.5 to 0.78. Ch1: Vin, Ch2: Iin, Ch3: Vo, Ch4: Io b Control to output voltage frequency response of the single-stage converter The dynamic behaviour of single-stage converter is tested under closed-loop conditions. Fig. 9 shows the dynamic response of the proposed converter against the load variation (the load changes from 115 to 50 W and again comes back to 115 W in Fig. 9a while the load changes from 90 to 20 W and again comeback to 90 W in Fig. 9b). As shown in Fig. 9, the proposed converter has a very fast dynamic response and the controller regulates the output voltage to its reference value without any initial drop in the output voltage which verifies the proposed converter do not have an RHPZ in its transfer function. Fig. 9Open in figure viewerPowerPoint Measured load transient response of single-stage converter during the load change back and forth under the input voltage of 25 V a 115 to 50 W (corresponding to the load current change from 3.12 to 1.33 A). Ch1: Vin, Ch2: Iin, Ch3: Vo, Ch4: Io b 90 to 20 W (corresponding to the load current change from 3.33 to 500 mA). Ch1: Vin, Ch2: Iin, Ch3: Vo, Ch4: Io The above procedure is repeated for a double-stage converter under open-loop conditions. The captured waveform at D = 0.75, Po = 105 W under open-loop control is shown in Fig. 10. Fig. 10a shows that the voltage stresses on switches are equal to the input voltage. Fig. 10b shows the voltage stress across the diodes. The voltage stresses across the diodes are low and equal to the input voltage that confirms the theoretical results. Fig. 10c shows the voltage across the capacitors. The voltages across C1, C2 and C4 are approximately equal to the input voltage and the voltage across C3 is about two times the input voltage which is consistent with the theoretical results. Finally, Fig. 10d shows the measured input voltage, input current, output voltage and output current. The output voltage is 66.5 V that is slightly lower than the theoretical results (68.75 V), because of the voltage drop across the diodes and other parasitic elements in the circuit. Fig. 10Open in figure viewerPowerPoint Measured waveforms at D = 0.75, Vin = 25 V, Vo = 66.5 V, Po = 105 W, Efficiency = 92% a Ch1: , Ch2: , Ch3: b Ch1: , Ch2: , Ch3: , Ch4: c Ch1: , Ch2: , Ch3: , Ch4: d Ch1: Vin, Ch2: Iin, Ch3: Vo, Ch4: Io Fig. 11 shows the measured efficiency curve against load current variation for the single-stage and double-stage converters. The maximum efficiency is about 93% for the single-stage converter when the load current is about 2.8 A and about 92% for double-stage converter when load current is 1 A. The efficiency of the double-stage converter is slightly lower than the single-stage converter as there are more power diodes in the double-stage converter. The efficiency of the KY converter [14] is higher compared with the proposed converter. However, the proposed converter is tested at high switching frequency that has a significant effect on the efficiency when compared with a low-frequency converter. In addition, the efficiency can be improved if the existing diodes are replaced with SiC, GaN diodes or synchronous rectifier to reduce the voltage drop. Compared with the inductor-less switched capacitor DC/DC converter [19], the proposed converter has higher efficiency. Fig. 11Open in figure viewerPowerPoint Efficiency against load current of the converter at the input voltage of 25 V 6 Conclusions A family of step-up DC/DC converters is introduced in this paper. The proposed converter has a simple and modular structure with only two active switches being utilised even in its Nth derivative. The converter has a fast dynamic response and the voltage stress on all semiconductor devices is low and equal to the input voltage. Therefore, low-voltage power switches can be used in the proposed converter that can lead to a lower cost. Similar to the synchronous buck converter, the proposed converter works only in CCM; therefore, a small inductor can be utilised. The proposed converter has a compact size, and it can be used in applications with very low allocated space such as portable devices. The performances of the single-stage and double-stage converters are verified in both simulation and experiments at 1 MHz switching frequency using GaN HEMT transistors. 7 References 1Hwu K., and Yau Y.: ‘A KY boost converter’, IEEE Trans. Power Electron., 2010, 25, (11), pp. 2699– 2703 (doi: http://doi.org/10.1109/TPEL.2010.2051235) 2Ismail E.H., Al-Saffar M.A., and Sabzali A.J. et al.: ‘A family of single-switch PWM converters with high step-up conversion ratio’, IEEE Trans. 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