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A VOLTAGE SCALING METHOD TOREDUCE POWER IN STATIC RAMS INDEEP SUBMICRON TECHNOLOGY

2014; Ess And Ess Research Publications; Volume: 3; Issue: 5 Linguagem: Inglês

2347-6710

H K Vidhyashree, K Thippeswamy,

VLSI and FPGA Design Techniques

This paper presents how power is reduced using voltage scaling method. By scaling the voltage down the power will be reduced but the low voltage increases the parametric failures like access, disturb and write. In this paper propose SRAM cell architecture with the application of low voltage for Lower ordered bits & nominal voltage for Higher ordered bits, because for multimedia applications like image, video and audio has inherent error tolerance. The proposed SRAM cell architecture is constructed using 45nm technology(transistor size, with Gate Length is 45nm ).Simulations results is shown how power is reduced for proposed SRAM cell architecture in comparison with standard SRAM cell. Along with power reduction the proposed SRAM cell architecture is tested under process and temperature variations.