Portal de Periódicos da CAPES

Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

2016; Elsevier BV; Volume: 73; Linguagem: Inglês

10.1016/j.aeue.2016.12.024

1618-0399

Min Chen, Yuanzhi Zhang, Chao Lü,

Advanced Data Compression Techniques

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4 [email protected] fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31–64% in hardware cost.