Efficient wide‐band droop compensation for CIC filters: ad hoc and reconfigurable FIR architectures
2017; Institution of Engineering and Technology; Volume: 53; Issue: 4 Linguagem: Inglês
10.1049/el.2016.3782
ISSN1350-911X
AutoresDavid Ernesto Troncoso Romero, Miriam Guadalupe Cruz Jiménez,
Tópico(s)Image and Signal Denoising Methods
ResumoElectronics LettersVolume 53, Issue 4 p. 228-229 Circuits and systemsFree Access Efficient wide-band droop compensation for CIC filters: ad hoc and reconfigurable FIR architectures D.E.T. Romero, Corresponding Author D.E.T. Romero detroncosoro@conacyt.mx CONACYT–ESCOM School, Institute IPN, Mexico City, 07738 MexicoSearch for more papers by this authorM.G.C. Jimenez, M.G.C. Jimenez Department of Electronics, Institute INAOE, Puebla, 72840 MexicoSearch for more papers by this author D.E.T. Romero, Corresponding Author D.E.T. Romero detroncosoro@conacyt.mx CONACYT–ESCOM School, Institute IPN, Mexico City, 07738 MexicoSearch for more papers by this authorM.G.C. Jimenez, M.G.C. Jimenez Department of Electronics, Institute INAOE, Puebla, 72840 MexicoSearch for more papers by this author First published: 01 February 2017 https://doi.org/10.1049/el.2016.3782Citations: 6AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract Novel finite impulse response architectures for wide passband droop compensation of cascaded integrator-comb filters are presented. Compared with the recent wide-band compensators introduced in the literature, the proposed systems achieve better passband droop correction with lower power dissipation, lower hardware utilisation and higher maximum frequency of operation, as validated with post-place-and-route information from FPGA-based implementations. Introduction The cascaded integrator-comb (CIC) filter from [1] is commonly used for decimation processes in cutting-edge applications such as multi-standard receivers or RF-to-baseband sigma–delta analogue-to-digital converters [2]. This is due to its simplicity, i.e. it does not require coefficients storage or multipliers. Its transfer function is HN(z, R), and its frequency response is HN(ejω, R) = HN(ω, R) × e–jωN(R–1)/2, with (1) (2)where R is the downsampling factor and N is the number of CIC stages. It is usual to have, after the CIC filtering process, a residual downsampling factor equal to 2 followed by a half-band filter arranged in polyphase components, which provides a band-edge shaping characteristic for the overall decimation scheme. The passband of interest in the total decimator is given between 0 and ωp = π/2R, and it is referred as wide passband (or simply wide-band if the context is clear). Unfortunately, the magnitude response of the CIC filter exhibits a droop over the passband, which increases when N increases, i.e. when a higher attenuation is specified for aliasing rejection. This droop is particularly undesirable in the wide-band scenario, and thus the improvement of the passband magnitude characteristic of CIC filters for this case has been recently investigated in [3, 4], where low-complexity multiplier-less designs have been developed (the previous research on the subject was addressed in [5-7], among others, where multipliers are avoided due to their undesirably high computational and implementation costs [8]). We pointed out in our preliminary work [3] that with a fourth-order compensator it is possible to achieve nearly four times better droop compensation with less than twice the computational complexity of the recent second-order compensators available in the literature. However, that work presented non-reconfigurable finite impulse response (FIR) architectures derived from a heuristic design method to find the multiplier-less coefficients. A different heuristic was recently employed in [4], where sixth-order compensators were designed for the typical cases of N: namely, between 1 and 6 (for N = 1, the compensator becomes a second-order filter). Even though a reconfigurable architecture for those Ns was mentioned, only ad hoc compensators were compared and reported without any post-place-and-route (PAR) information. In this Letter, we present a fourth-order, multiplier-less, FIR reconfigurable architecture for wide-band compensation of CIC filters, whose main attribute is that it has arisen from an optimised design procedure over a discrete canonical signed digit (CSD) coefficients space. Our optimisation scheme is a particle swarm optimisation (PSO) algorithm that allows to derive easily either wide-band or narrow-band FIR compensators with different orders and different number of non-zero digits for the coefficients. The proposed system, which can be configured for N between 1 and 6, provides the minimum passband deviation with the best possible choice of multiplier-less coefficients, guarantying a computational complexity of ten additions at most. Moreover, we also present ad hoc designs suitable for a fixed N, where a common sub-expression elimination (CSE) method was used to save additions. Proposed PSO-based design procedure The proposed design procedure, based on method [9], consists in finding the optimal vector g* of finite-precision compensator coefficients with eight bits for the fractional part. Every coefficient has only a prescribed number of non-zero SDs in order to set a priori an upper bound on the total number of required addition or subtraction operations. The constraint of having an amplitude response equal to 1 at ω = 0 in the compensated filter is also added. Thus, the optimisation problem is (3)where G(ω, g) is the amplitude response of the compensator. To solve this problem, we developed a MATLAB function of the form g = f(L, N, nz, F) which provides in g the multiplier-less coefficients of a compensator of even order L, suitable for a CIC filter with N stages. Each coefficient has nz non-zero SDs at most and F represents the residual downsampling factor after the CIC filtering process. For the proposed structures, we have set L = 4, nz = 3, F = 2 and N between 1 and 6 (these values of N form the benchmark of the previous literature and cover attenuations typically specified). It is worth highlighting that PSO has been used as optimisation algorithm in order to properly search into the non-uniform CSD space, where the traditional integer linear programming does not work. Proposed ad hoc solutions We have obtained different compensators whose integer coefficients g(0), g(1) and g(2) are shown in Table 1 [since these are linear phase Type-1 filters, we have g(0) = g(4) and g(1) = g(3)]. CSE has been carried out on the coefficients in order to save additions. Fig. 1 shows the corresponding architecture for N = 4 (the other architectures can be easily obtained from Table 1). Fig 1Open in figure viewerPowerPoint Wide-band compensator for N = 4 Table 1. Integer coefficients for wide-band compensators (gain is 28) Sub-expressions: x1 = 22–1 x2 = 22 + 1 x3 = 23–1 x4 = 23 + 1 N Compensator coefficients 1 g(0) = 2 g(1) = –(2x4) g(2) = 25x4 2 g(0) = x2 g(1) = –(23x2) g(2) = 26x2 + 2x1 3 g(0) = x4 g(1) = –(26 + 1) g(2) = 29–24x4 4 g(0) = 2x3 g(1) = –(25x1–2) g(2) = 27x1 + 25 5 g(0) = 24 + x2 g(1) = –(27 + 1) g(2) = 29–23x2 6 g(0) = 25–x1 g(1) = –(27 + 23x2) g(2) = 29 + 25–2x2 Proposed reconfigurable solution In this case, we have taken advantage of the fact that g(2) = 28–2[g(0) + g(1)] holds, thus only g(0) and g(1) are adjustable as follows: g(0) = 2a0 + (–1)b0 × c0 × 22 + (–1)d0 × 2e0; g(1) = 2a1 + (–1)b1 × c1 × 25 + (–1)d1 × 2e1. The resulting architecture is presented in Fig. 2 (just a configurable coefficient is detailed). The programmable shifts an and en, with n {0, 1}, are made via multiplexers (not shown for simplicity), whereas bn and dn represent adder/subtractor selectors. These parameters are configured as shown in Table 2. Fig 2Open in figure viewerPowerPoint Reconfigurable wide-band compensator Results For a detailed comparison, the proposed filters and the ones from [4] have been synthesised into the Altera's Cyclone-IV EP4CE115F29C7 FPGA chip, currently used on the popular (mainly among the academic community) DE2-115 development kit, with overflow-aware sizes in their internal buses. The operation of the filters was simulated with an 8 bit cosine signal of fs/14 MHz as input, sampled at fs MHz, with fs = 160 for the ad hoc architectures and fs = 80 for the reconfigurable architectures (which are slower). To contrast our proposed reconfigurable compensator with that of method [4], we have made adjustable for N the multiplier-less coefficients (called B1 and B2) of the ad hoc compensators in [4], just as we did with coefficients g(0) and g(1) of our proposed solution. N was set between 1 and 6 (as documented in [4]). The value change dump information generated by ModelSim was used in the power play power analyser to estimate power dissipation with high level of confidence, and TimeQuest Timing Analyser was employed for the estimation of performance, using the slow 85C timing model (the worst-case scenario). Table 2. Values for reconfiguration parameters (dc means do not care) N a0 b0 c0 d0 e0 a1 b1 c1 d1 e1 1 2 dc 0 1 1 4 dc 0 0 1 2 2 dc 0 0 0 5 dc 0 0 3 3 3 dc 0 0 0 6 dc 0 0 0 4 4 dc 0 1 1 7 1 1 1 1 5 4 0 1 0 0 7 dc 0 0 0 6 5 1 1 0 0 7 0 1 0 3 Tables 3–5 summarise the post-PAR information for the ad hoc compensators and Table 6 contains the post-PAR information for the reconfigurable compensators (note that LE means logic elements of the FPGA chip). Table 7 shows the maximum passband deviations, which have been calculated with R = 16 (in fact the compensation is practically not affected by R). The advantages of the proposed architectures are evident. For N = 1, the proposed solution achieves nine times better compensation characteristics with just 1.5 times the complexity of the second-order compensator from [4]. For other Ns, the passband deviations are better, in general (except for N = 6, where the deviation of the proposed system is slightly worst), and the proposed solutions are faster and more power- and area-efficient. Table 3. Maximum frequency of operation for ad hoc cases (megahertz) N = 1 N = 2 N = 3 N = 4 N = 5 N = 6 [4] 194.4 130.2 123.8 120.2 126.9 133.2 Proposed 250 194.8 208.7 187.5 178.4 170.5 Table 4. Hardware utilisation for ad hoc cases (LEs) N = 1 N = 2 N = 3 N = 4 N = 5 N = 6 [4] 55 174 173 182 215 208 Proposed 81 115 115 123 132 150 Table 5. Estimated power dissipation for ad hoc cases [milliwatts (mW)] N = 1 N = 2 N = 3 N = 4 N = 5 N = 6 [4] 162 178 179.3 168.4 179.6 181.9 Proposed 163.9 167.4 169.5 168.3 170.3 170.8 Table 6. Post-PAR results for reconfigurable compensators Power dissipation (mW) Hardware usage (LEs) Max. freq. of operation (MHz) [4] 153.7 371 96.9 Proposed 150.1 331 164.3 Table 7. Maximum passband deviation (dB) N = 1 N = 2 N = 3 N = 4 N = 5 N = 6 [4] 0.063 0.028 0.038 0.051 0.066 0.06 Proposed 0.007 0.027 0.024 0.036 0.053 0.077 Conclusion Owing to the proposed PSO-based optimisation framework, the ad hoc architectures can achieve improved droop corrections with up to 40% of reduction in hardware utilisation, 6% of reduction in power dissipation and 30% of increase in maximum frequency of operation compared with the recent ad hoc compensators available in the literature. The proposed reconfigurable solution achieves 69% of increase in maximum frequency of operation, 3% of reduction in power dissipation and 11% of reduction in hardware utilisation. As a future work, we will use our MATLAB-based PSO algorithm to investigate the best trade-offs between complexities and droop corrections of wide- and narrow-band compensators with different orders and different number of non-zero digits in their coefficients. Acknowledgment M.G.C. Jimenez is grateful to CONACYT for the scholarships nos. 224191, 290842 and 290935. The authors acknowledge the particular interest of G.J. Dolecek on their PSO MATLAB-based code for the design of optimal FIR compensators (she received this code for personal use on 30 April 2016). References 1Hogenauer, E.B.: ‘An economical class of digital filters for decimation and interpolation’, IEEE Trans. Acoust. Speech Signal Process., 1981, 29, (2), pp. 155– 162 (https://doi/org/10.1109/TASSP.1981.1163535) 2Fa-Long, L.: ‘ Digital front-end in wireless communications and broadcasting: circuits and signal processing’ ( Cambridge University Press, New York, USA, 2011) 3Jimenez, M.C., Romero, D.E.T., Dolecek, G.J., Laddomada, M.: ‘ Wide-band CIC compensators based on amplitude transformation’. IEEE Int. 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