Digital impedance pilot relaying scheme for STATCOM compensated TL for fault phase classification with fault location
2017; Institution of Engineering and Technology; Volume: 11; Issue: 10 Linguagem: Inglês
10.1049/iet-gtd.2016.1670
ISSN1751-8695
AutoresArvind R. Singh, Nita R. Patne, Vijay S. Kale, Piyush Khadke,
Tópico(s)HVDC Systems and Fault Protection
ResumoIET Generation, Transmission & DistributionVolume 11, Issue 10 p. 2586-2598 Research ArticleFree Access Digital impedance pilot relaying scheme for STATCOM compensated TL for fault phase classification with fault location Arvind R. Singh, Corresponding Author Arvind R. Singh arvindsinghwce@gmail.com Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this authorNita R. Patne, Nita R. Patne Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this authorVijay S. Kale, Vijay S. Kale Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this authorPiyush Khadke, Piyush Khadke Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this author Arvind R. Singh, Corresponding Author Arvind R. Singh arvindsinghwce@gmail.com Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this authorNita R. Patne, Nita R. Patne Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this authorVijay S. Kale, Vijay S. Kale Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this authorPiyush Khadke, Piyush Khadke Department of Electrical Engineering, VNIT, Nagpur, Maharashtra, 440010 IndiaSearch for more papers by this author First published: 07 July 2017 https://doi.org/10.1049/iet-gtd.2016.1670Citations: 16AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract This study presents calculation of fundamental frequency-based per phase digital impedance pilot relaying (DIPR) scheme for static synchronous compensator (STATCOM) compensated transmission line (TL) using two end synchronised measurement. DIPR involves computation of absolute value of ratio of estimated phasor sum of voltages to the phasor sum of currents of both ends. DIPR inherently differentiate between internal and external faults on the line. For all internal faults, computed value of DIPR ratio is equivalent to system and TL impedance value whereas for external faults, it is equal to line capacitance impedance value. This novel pilot relaying scheme is easy to set once the system parameters are estimated and has the ability to detect all types of faults and correctly classify faulty phase with mid-point connected STATCOM on TL. This scheme is immune to effect of STATCOM compensation mode, level of injection and its dynamic response. Also it is not affected by line charging capacitive current and fault transient resistance. The fault distance is estimated using the STATCOM current injection information for various types of fault with high accuracy, considering maximum fault resistance of 20 Ω. Accuracy and effectiveness of this scheme is evaluated in EMTDC/PSCAD simulation for 230 kV, 300 km, mid-point STATCOM compensated TL and in hardware setup with mid-point STATCOM on 100 V supply voltage having 200 km TL in offline mode. Results bring out the robustness, reliability and superiority of proposed novel pilot relaying scheme with fault location algorithm. 1 Introduction The protection of transmission line (TL) involves fault detection and classification for fast disconnection and restoration of faulted line to maintain the power system stability and reliability [1]. To enhance the power transfer capability, flexible AC transmission system devices were introduced [2]. Static synchronous compensator (STATCOM) has ability to offer inductive as well as capacitive compensation [3]. These devices have fast response which may overlap with protection system response time leading to mal-operation of relaying devices connected in the system [4]. Distance relay mainly mal-operates in the form of under-reaching (UR) or over-reaching (OR) the faults in the presence of STATCOM device [5–9]. The coherent conclusion is early tripping for no zone faults (OR), delayed tripping for in zone faults (UR) and wrong calculation of fault location [10, 11]. The fault location algorithm was proposed in [8] using the optimisation technique. However, knowledge of the fault type is required, which has not been reported in [8]. Adaptive mho distance zone relaying scheme with static var compensator (SVC) on line was proposed in [9] wherein, the new formula to calculate new setting was derived. However, fault classification algorithm problem was not addressed. Pilot relaying schemes are free from the UR or OR problem [8]. Conventional pilot relaying is based on differential current algorithm which detects faults with low-resistance but mal-operate to detect high-resistance faults [10, 12]. In [13], fault component integrated impedance (FCII)-based pilot protection algorithm had been proposed for uncompensated TL. FCII algorithm can be used for shunt compensation but variable impedance offered by STATCOM in phases can be seen as fault component due to which healthy phases may be classified as faulty phases. Integrated impedance-based pilot relaying algorithm had been proposed for series-compensated line in [12]. This algorithm claimed to detect all faults having low resistance but it mal-operates for faults with high-resistance. Also, in [12, 13], effect of asymmetrical faults on healthy phases has not been discussed. In [12], fault component integrated power (FCIP)-based pilot relaying was presented for internal and external fault detection and phase classification. However, sign convention presented for fault detection does not hold valid for external faults in shunt compensated line. In [14], authors have used sequence component network to calculate superimposed sequence components of voltage and current for SVC compensated TL. The work presented is not suitable for STATCOM compensated TL as compensation remains unaffected due to drop in voltage. In this work, digital impedance pilot relaying (DIPR) using phasors is proposed which is highly reliable for faults with high as well as low resistance. DIPR involves computation of absolute value of ratio of estimated phasor sum of voltages to phasor sum of currents of both ends. Its value is large for external faults and small for internal faults. Hence, it can be used to differentiate between internal–external faults as well as it classifies faulty phase very accurately. The terminal voltages and currents of STATCOM bus are estimated using the information of STATCOM impedance variation and nearest bus voltage having high value. DIPR algorithm requires high-speed data communication link between both ends and measurement data must be GPS time stamped to nullify error [11]. The proposed pilot relaying algorithm is most suitable for STATCOM compensated TL and accuracy of this algorithm is validated using PSCAD EMTDC [15] and with hardware setup in offline mode. 2 Test system and STATCOM modelling The four generators and three TL power system with STATCOM connected at mid-point of line-1 is as shown in Fig. 1. STATCOM is modelled as 12-pulse voltage source converter. The control system of this device has two modes of operation, namely voltage regulation mode and reactive power injection mode. In voltage regulation mode, compensating device regulates the connection point voltage to maintain 1 per unit voltage in all conditions. Reactive power required to be either absorbed or injected into system. For reactive power injection mode, the amount of reactive power need to be injected is fixed (inductive or capacitive) irrespective of connection point voltage in this study. To study the effect of shunt compensating device operation mode on fault transient signal, the reactive power injection control mode is used. Transmission line is modelled using the structural information of tower data, circuit conductor data, circuit ground wire data, circuit conductor bundling data and phase connection considering frequency-dependant phase model in PSCAD. The fault current is measured at bus M and N with ANSI/IEEE 1200:5, class C400 CT model has been used to obtain the realistic CT response in simulations. Fig. 1Open in figure viewerPowerPoint Test system with mid-point STATCOM 3 DIPR-based scheme for shunt compensated TL 3.1 DIPR for uncompensated TL for internal fault The equivalent circuit for internal fault on TL without compensation is shown Fig. 2 (i). TL pi-equivalent model is considered for analysis. Considering a fault at point F with fault current . and are TL positive sequence impedance between point F and end bus M and N, respectively. and are equivalent system impedances connected at bus M and N, respectively. and are positive and zero sequence impedance of TL. , , and are voltage and current phasor estimated at bus M and N, respectively. Per phase DIPR ratio for internal fault without compensation is defined as (1) where Fig. 2Open in figure viewerPowerPoint Equivalent circuits (i) For internal fault without compensation, (ii) For internal fault with shunt compensation, (iii) For external fault with shunt compensation 3.2 DIPR for shunt compensated TL with internal fault In this case, STATCOM is installed at the mid-point of TL and internal fault is considered at point F as shown in Fig. 2 (ii). During internal fault, capacitive current is much smaller than line and fault currents. Also, capacitive impedance is higher than that of TL impedance as well as system impedances. To carry out analysis in simplified manner, shunt charging currents at both buses is neglected in derivation. Let p be ratio of fault point impedance from bus terminals to the impedance of whole line length, then (2) For internal faults with shunt compensation, it has two conditions of fault point. For (3) (4) For (5) (6) Fault current and voltage to calculate bus terminal voltage and current is given as (7) (8) (9) Substituting the values in (1) gives result as (10) It is considered that the impedance angles of the source and TL in high-voltage power transmission system are close to . Whereas impedance angles , , and are approximately equal to each other. The values of and are always higher than the values of and due to the contribution of . Hence, and , due to . Therefore modifying (10) based on following assumptions and substituting as and as to get following inequalities conditions for internal fault: (11) From (11), it is evident that per phase DIPR ratio for internal fault reflects equivalent system and TL impedances and DIPR ratio has effect of equivalent impedance offered by STATCOM. 3.3 DIPR for shunt compensated TL with external fault Current in per phase DIPR ratio calculation have only capacitive current value during external fault. The circuit diagram for external fault with STATCOM is shown in Fig. 2 (iii). The current flowing from both buses in the TL during external fault are and . From Fig. 2 (iii), the per phase DIPR ratio currents can be found as (12) (13) (14) From (14), it is evident that whenever external fault occurs, the DIPR ratio value is equal to and has higher value in comparison to system and TL equivalent impedance (15) 3.4 Digital pilot protection scheme threshold setting and fault location The analysis presented leads to conclusion that if fault is external fault, DIPR ratio gives value which is equal to capacitive impedance of TL. Per phase DIPR ratio value is always higher than the per phase system and TL equivalent impedance values for all external faults. Whereas for all internal faults per phase DIPR ratio gives value equal to per phase system, STATCOM and TL equivalent impedance and have less value. Considering 300 km, 230 kV, transmission system without compensation, the capacitive impedance value is ∼1000 Ω. The problem arises due to connected STATCOM device at mid-point of TL and it compensates equivalent capacitive impedance severely. It was observed in simulation studies that when STATCOM injects capacitive compensation of 100 MVAr, DIPR ratio value is reduced from normal value and is in range of 600–800 Ω under no fault condition. When it injects inductive compensation of 100 MVAr, the DIPR ratio value increased from normal value and is in the range of 1500–1700 Ω under no fault condition. With above discussion and simulation studies, the conclusion drawn is that setting for DIPR ratio should be in the range of 300–500 Ω. The TL absolute value of impedance is ∼150 Ω for 300 km line length and for detection of 200 Ω high-resistance faults including STATCOM compensation effect, the value of 350 Ω is set as threshold for DIPR setting in this study system [16]. To maintain the reliability and sensitivity of this new pilot protection algorithm absolute value of per phase DIPR ratio is used for fault detection. For universal per phase DIPR ratio setting for any line or different system is shown in (15). This new DIPR algorithm can detect, classify faulty phases for all faults without and with fault resistance up to 200 Ω with no false tripping. DIPR fault phase detection scheme combining with fault location estimation algorithm become more reliable and realistic for actual system implementation. It is possible to use fault location estimation algorithm by calculating the mid-point voltage from TL model and shunt injected current from STATCOM characteristics. To calculate the injected current by STATCOM from its V –I characteristics, voltage at its connection point needs to be calculated using pi-model TL voltage distribution formula. The STATCOM voltage connected at mid-point of TL is given as (16) (17) where x is phases a, b and c ; y is M or N (sending or receiving end); is the slope of STATCOM characteristics equal to 0.03%; is the coupling transformer reactance 0.1 p.u.; is the STATCOM reactive power injection reference. To calculate the STATCOM voltage at bus ends, higher value of voltage from (16) should be used due to the uncertainty of fault point. Using the V –I characteristics of STATCOM shown in Fig. 3, injected current is calculated using (17) based on reactive reference in the study. Using calculated STATCOM injected current, the per unit fault distance from any end of line for any phase, considering full length is given as [11] (18) where , and is the zero sequence component of current. Fig. 3Open in figure viewerPowerPoint STATCOM characteristics for injected current calculation obtained from simulation In next section, simulation results are presented for proposed DIPR algorithm validation and evaluation. 4 Simulation results and discussion The proposed new algorithm is verified by PSCAD/EMTDC simulation with fault and GPS time stamped sampled data generation at both the ends. Simulation time is assumed same as GPS time for time tagging. The pilot relay is implemented in MATLAB m-file programming with proposed threshold value for internal and external faults with and without compensation to verify the setting criterion. The data are fetched with sampling rate of 1 kHz from CT and PT at both the ends as explained in Section 2 and shown in Fig. 1. It is assumed that fast data communication channel is available without any intentional delay at both ends. The proposed relay is implemented at bus M with GPS synchronised data received from N bus. Fig. 4 shows the voltage and current waveform with STATCOM at mid-point of TL for internal A–g fault at 160 km of TL from bus M and having fault resistance of 0.1 Ω created at 0.604 s in PSCAD simulation. The STATCOM injection is initiated into system at 0.2 s for A–g fault with reactive power reference of 100 MVAr (inductive). Fig. 5 (i) presents the absolute value of DIPR ratio calculated for internal A–g fault using (11) for each phase. The DIPR threshold has been shown in Fig. 5 (i) and the same convention has been considered throughout. Fig. 4Open in figure viewerPowerPoint Internal A–g fault at 160 km of line with fault resistance 0.1 Ω, created at 0.604 s (i) Voltage waveform, (ii) Current waveform Fig. 5Open in figure viewerPowerPoint Internal A–g fault at 160 km of line with fault resistance 0.1 Ω (i) Per phase DIPR ratio, (ii) Per phase relay trip decision The trip decision is shown in Fig. 5 (ii) for each phase with DIPR threshold 350 Ω. In relay design, flag counter is initiated when DIPR ratio value is less than threshold value. When counter value reach to 5, trip decision is issued. For an A–g fault, the DIPR ratio value drops down to 275.2 Ω at 0.609 s, less than set threshold value. Hence, initiating the counter in the relay programming, whose value changes from 0 to 1 at 0.614 s as observed from Fig. 5 (ii). Healthy phase values remain high as depicted in Fig. 5 (ii) with data tag. DIPR calculated ratio values and phase wise trip decisions are shown in Fig. 6 for ABC fault at 170 km of TL with negligible fault resistance with maximum inductive compensation. Respective values w. r. t. time are shown in the figure for better illustration. It is evident from Figs. 5 and 6 that when STATCOM injects maximum inductive compensation, per phase DIPR ratio value is in the range of 1500–1700 Ω and when fault occurs, per phase DIPR ratio value is less than threshold value of equivalent system and TL impedance value. The effect of STATCOM injection also affects equivalent values but does not reduce to zero value. Fig. 6Open in figure viewerPowerPoint ABC internal fault at 170 km of line with 0.1 Ω fault resistance created at 0.604 s with maximum inductive compensation (i) Per phase DIPR ratio with inductive injection, (ii) Per phase DIPR ratio with capacitive injection It is evident from Fig. 6 (i) that when STATCOM injects maximum inductive compensation, per phase DIPR ratio value is in the range of 1500–1700 Ω and when fault occurs, per phase DIPR ratio value is less than threshold value of equivalent system and TL impedance value. Fig. 6 (ii) shows DIPR calculated ratio value for each phase in case of ABC internal fault with negligible resistance with maximum capacitive compensation injected by STATCOM. Before the occurrence of fault, calculated DIPR ratio value is in the range of 600–800 Ω and after fault it become less than threshold set value, trip decision is issued. Hence, it can be deduced that proposed algorithm for fault phase classification is not affected by inductive or capacitive compensation. Also, per phase fault detection time is approximately half cycle taking into account flag counter time and can be made faster by reducing the set flag counter value. The rigorous simulation studies have been performed considering different fault location with and without fault resistance. The proposed algorithm is found to be accurate in detecting the faults and classifying the faulty phases. Fig 7 (i) shows the current waveform of CT primary and secondary for A–g fault at distance 0.1 km ahead of bus M with 0.1 Ω fault resistance created at 0.604 s. As the fault is very close to the sending end measurement device, the saturation in the CT is observed. It is due to the severe fault current caused due to close-in fault and results in delayed fault detection. Fig. 7 (ii) shows the current waveform for AB–g fault at distance 149.9 km ahead of bus M with 0.1 Ω fault resistance created at 0.604 s. The saturation is observed in third cycle and provides enough time to detect and identify the fault and faulty phase. In worst case scenario, severe CT saturation may lead to mal-operation of relaying device. However, in case of the proposed relaying scheme which uses two end measurements, the problems in fault detection due to CT saturation are minimum. Fig. 9 shows the current waveform of CT primary and secondary for BC–g fault at distance 0.1 km before of bus N with 0.1 Ω fault resistance created at 0.604 s. The effect of STATCOM injection is clearly observed in the current waveform during the fault period. Fig. 7Open in figure viewerPowerPoint Current waveform of CT primary and secondary for (i) A–g fault at distance 0.1 km ahead of bus M with 0.1 Ω fault resistance created at 0.604 s, (ii) AB–g fault at distance 149.9 km ahead of bus M with 0.1 Ω fault resistance created at 0.604 s The proposed relaying algorithm is verified for faults near to bus at M, N and STATCOM connection point. Fig. 8 (i) shows the fault at 0.1 km ahead of bus M with fault resistance of 0.1 Ω. The DIPR scheme is able to discriminate close-in fault which is very near to bus M. Fig. 8 (ii) shows fault very near to STATCOM bus at 149.9 km ahead of bus M with minimum fault resistance. It is observed that, as the fault is near to the mid-point of the TL, the relaying algorithm detects the fault within one cycle. Hence, for faults near to STATCOM bus, the proposed relaying algorithm detects the fault accurately but requires high detection time as compared to other location fault points. For closein faults, severe CT saturation is observed as shown in Fig. 7 and Fig. 9 and as a result full cycle DFT phasor estimation has error and leads to larger fault detection time. Fig. 10 (i) shows fault very near to bus N at 0.1 km before the bus. The relaying algorithm gives accurate detection and detection time is within half cycle. Similarly, Fig. 10 (ii) shows results for external fault 0.1 km ahead of bus N. As observed from results, the proposed relaying algorithm is able to discriminate close-in external faults accurately. The STATCOM compensation is maximum 100 MVAr capacitive for results shown in Figs. 8 and 10. Fig. 8Open in figure viewerPowerPoint Per phase DIPR ratio for internal faults (i) A–g fault at distance 0.1 km ahead of bus M with 0.1 Ω fault resistance created at 0.604 s, (ii) AB–g fault at distance 149.9 km ahead of bus M with 0.1 Ω fault resistance created at 0.604 s Fig. 9Open in figure viewerPowerPoint Current waveform of CT primary and secondary for BC–g fault at distance 0.1 km before bus N with 0.1 Ω fault resistance created at 0.604 s Fig. 10Open in figure viewerPowerPoint Per phase DIPR ratio for close-in faults (i) BC–g fault at distance 0.1 km before of bus N with 0.1 Ω fault resistance created at 0.604 s, (ii) ABC fault at distance 0.1 km ahead of bus N with 0.1 Ω fault resistance created at 0.604 s To evaluate the performance of the proposed algorithm for the external faults, A–g and ABC faults are created after bus N, respectively, with maximum capacitive compensation. Figs. 11 (i) and (ii) show the calculated per phase DIPR ratio values for A–g and ABC external faults. The impedance value for both fault condition lies above threshold value and trip decisions are not issued in both cases. Fig. 11Open in figure viewerPowerPoint Per phase DIPR ratio for external faults (i) A–g fault at distance 20 km ahead of bus N with 0.1 Ω fault resistance created at 0.604 s, (ii) ABC fault at distance 50 km ahead of bus N with 0.1 Ω fault resistance created at 0.604 s Table 1 shows the calculated absolute values of DIPR ratio 0.1 Ω fault resistance considering maximum inductive shunt compensation of 100 MVAr for internal and external faults. Table 2 shows calculated absolute values of DIPR ratio with 0.1 Ω fault resistance considering maximum capacitive shunt compensation of 100 MVAr for internal and external faults. From both the tables, it is observed that proposed DIPR algorithm performs accurately for STATCOM in inductive as well as capacitive compensation mode. Table 3 shows dependability of proposed scheme with fault resistance of 100 Ω for internal and external faults with STATCOM compensation. Table 1. DIPR ratio with 0.1 Ω fault resistance for maximum inductive STATCOM compensation Fault location, km Fault type 10 A–g 36.92 1898 1506 BC–g 3398 33.29 34.51 ABC 29.68 29.89 29.73 100 A–g 107.3 2121 1782 BC–g 537.5 76.18 77.10 ABC 67.07 67.68 67.23 200 A–g 106.7 1845 1851 BC–g 1186 82.78 82.86 ABC 72.12 72.19 72.14 280 A–g 44.24 1770 852 BC–g 3102 40.02 40.66 ABC 33.64 33.59 33.39 external 90 A–g 1449 1605 1647 BC–g 1664 1523 1529 ABC 1527 1576 1578 Table 2. DIPR ratio with 0.1 Ω fault resistance for maximum capacitive STATCOM compensation Fault location, km Fault type 10 A–g 40.68 566.4 520.5 BC–g 554.9 33.59 33.57 ABC 31.32 31.84 31.06 100 A–g 110.2 553.5 608.6 BC–g 522.3 86.17 87.57 ABC 68.65 68.85 68.07 200 A–g 117.7 439.5 492.5 BC–g 421.9 88.35 88.45 ABC 72.03 72.45 72.67 280 A–g 46.78 432 502.4 BC–g 496.5 39.6 40.8 ABC 36.25 36.28 36.18 external 90 A–g 660.3 640.1 664.3 BC–g 559.7 621.4 615.4 ABC 565.4 565.8 565.1 Table 3. DIPR ratio with 100 Ω fault resistance for STATCOM compensation Fault location, km Fault type 10 A–g 206.6 1788 1529 BC–g 1636 201.8 201.1 ABC 77.71 77.71 77.71 100 A–g 238.5 1930 1426 BC–g 1747 215.9 214.8 ABC 92.47 92.45 92.1 200 A–g 227.4 648.4 648.7 BC–g 514.5 208 209 ABC 97.5 97.8 97.1 280 A–g 203.1 704.2 696.7 BC–g 615.8 203.5 203.7 ABC 76.23 76.32 76.29 external 90 A–g 711 710.4 711.6 BC–g 663.9 667.5 713.6 ABC 601.2 601.9 601.3 Table 4 shows % error in fault distance estimation using (17) for STATCOM compensated TL. The maximum error observed from Table 4 is 0.53% for 300 km TL. Results presented in Table 4 are for fault distance estimation with 20 Ω fault resistance for various faults and locations. For fault having high resistance up to 200 Ω, error may increase up to 2% due to the effect of STATCOM compensation as observed in simulation studies. Table 4. Fault distance estimation using (17) for STATCOM compensated/TL with 20 Ω fault resistance Fault location, km Fault type Estimated fault distance, km % error 160 A–g 160.5 0.17 BC–g 159.8 −0.23 AB 160.2 0.07 ABC 160.1 0.03 200 A–g 199.8 −0.07 BC–g 201.3 0.43 AB 199.3 −0.23 ABC 200.9 0.3 240 A–g 241.3 0.43 BC–g 241.8 0.53 AB 240.6 0.20 ABC 241.6 0.53 Table 5 shows the results for fault with 10 Ω resistance for three different installation points of STATCOM. The tabulated results show per phase DIPR ratio for internal as well as external fault. It is observed from Table 5 that when STATCOM is installed at end points, the phase having fault shows very less value while other phases DIPR ratio value is much higher than the threshold setting. Similar observations can be concluded when STATCOM is present at mid-point of TL. Table 6 shows the per phase DIPR ratio for close-in fault with STATCOM installed at mid-point of the TL and injecting maximum capacitive compensation. It is observed from the tabulated results that proposed relaying algorithm gives accurate discrimination for close-in faults as well as external faults. Hence, proposed relaying algorithm is reliable and dependable for all types of internal and external faults. Table 5. Per phase DIPR ratio with 10 Ω fault resistance for different installation STATCOM point with maximum capacitive compensation STATCOM installation point Fault location, km Fault type AtbusM 50 A–g 92.50 1939.40 1879.1 BC–g 1884.10 64.53 63.63 ABC 53.16 53.27 52.98 100 A–g 116.30 2017.90 2000.98 BC–g 1951.50 75.22 74.89 ABC 65.91 65.31 64.89 200 A–g 116.72 2022.90 1999.46 BC–g 1989.90 75.79 74.86 ABC 65.72 66.53 64.74 280 A–g 52.90 2037.5 2037.3 BC–g 2043.10 71.76 70.02 ABC 32.63 32.83 31.97 Ext.10 A–g 2047.8 2047.3 2047.1 BC–g 1982.7 1983.1 1982.9 ABC 1853.1 1851.9 1852.7 Atmid-point 50 A–g 85.32 483.25 484.81 BC–g 507.33 58.16 57.96 ABC 49.91 50.49 49.18 100 A–g 120.27 564.01 618.24 BC–g 531.25 95.89 97.61 ABC 73.62 72.89 73.87 200 A–g 123.39 434.24 454.23 BC–g 451.90 94.97 94.85 ABC 76.78 78.68 77.81 280 A–g 53.37 471.65 475.97 BC–g 504.74 44.17 43.86 ABC 45.29 44.23 44.84 Ext.10 A–g 552.8 609.36 607.36 BC–g 488.04 486.03 487.15 ABC 487.39 487.54 486.98 AtbusN 50 A–g 93.74 1944.7 1923.6 BC–g 1896.8 64.09 63.12 ABC 53.30 55.11 54.89 100 A–g 117.75 2021.9 2019.8 BC–g 1961.2 75.23 74.80 ABC 65.16 65.54 64.95 200 A–g 114.88 2021 2017.9 BC–g 1998.7 74.67 73.89 ABC 62.96 61.47 62.42 280 A–g 50.65 2041.7 2040.3 BC–g 2037.4 41.34 40.37 ABC 31.52 30.38 30.68 Ext.10 A–g 2051.1 2053.6 2052.3 BC–g 1915.9 1912.6 1913.3 ABC 1838.3 1839.1 1838.9 Table 6. Per phase DIPR ratio with 1 Ω fault resistance for different close-in faults with mid-point STATCOM and maximum capacitive compensation Fault location, km Fault type 2 A–g 45.89 493.89 491.77 BC–g 469.80 41.97 42.08 ABC 38.11 38.16 37.84 4 A–g 46.42 495.52 493.17 BC–g 471.39 42.14 43.24 ABC 39.87 39.64 38.45 6 A–g 46.94 496.97 495.51 BC–g 471.08 43.31 44.93 ABC 41.10 40.84 40.48 146 A–g 136.46 435.23 432.78 BC–g 431.68 135.40 136.19 ABC 78.41 78.85 78.69 148 A–g 137.36 419.55 421.24 BC–g 419.63 76.83 76.43 ABC 74.57 74.09 74.36 152 A–g 137.56 419.88 420.85 BC–g 420.17 76.97 79.01 ABC 74.49 74.97 74.86 154 A–g 136.66 435.71 433.50 BC–g 431.68 78.45 78.93 ABC 78.53 78.12 78.83 294 A–g 37.27 414.94 413.72 BC–g 411.29 36.43 35.89 ABC 31.98 31.21 31.54 296 A–g 36.16 413.19 412.40 BC–g 409.94 35.24 34.22 ABC 30.24 30.31 30.46 298 A–g 34.24 411.65 411.49 BC–g 406.85 33.87 33.14 ABC 28.60 28.71 28.66 Ext.2 A–g 544.85 536.97 543.99 BC–g 422.44 416.69 413.71 ABC 409.98 409.39 409.55 Ext.4 A–g 545.96 538.27 545.44 BC–g 422.79 416.89 415.17 ABC 410.13 410.86 410.75 Ext.6 A–g 546.43 538.97 546.27 BC–g 423.21 417.56 415.93 ABC 410.27 411.09 410.97 5 Hardware setup and per phase fault detection algorithm validation 5.1 Two-machine system hardware details Two-machine system with STATCOM controller hardware setup is shown in Fig. 12 for proposed per phase DIPR algorithm validation. The sending end generator has on-board AVR with shunt DC motor as a prime mover having capacity of 3 kW. The receiving end generator has manual excitation control with VFD induction motor as a prime mover having 2 kW capacity. STATCOM controller is connected at the mid-point of 200 km TL. The STATCOM has DSP-based closed loop controller to regulate mid-point voltage to 1 p.u. Transmission lines are pi-equivalent models with four sections, namely 30, 70, 70 and 30 km. CT6841 sensor used for current measurements are HIOKI make. Power analyser 3390 HIOKI make is used as real-time data recorder for acquiring current and voltage signals for different fault cases. The real-time data recorder has sampling rate of 10 kHz and has four voltage and current channels. Due to the limited number of channels and considering the same time stamping on both end measurements on two phases of each bus are recorded for algorithm validation. The proposed faulty phase detection algorithm is based on per phase and fault location algorithm requires measurement of all the three phases, hence only faulty phase detection and classification algorithm is validated in hardware. Recorded samples of fault events are fed to MATLAB programme which implements the proposed relaying algorithm at 1 kHz after downsampling in offline mode. The recorded samples are used to calculate voltage and current phasors using recursive discrete Fourier transform. Fig. 12Open in figure viewerPowerPoint Two-machine system with STATCOM controller hardware setup 5.2 DIPR per phase fault detection algorithm validation for two-machine system In proposed per phase DIPR ratio-based fault phase detection algorithm, the threshold value is decided after observing >100 recorded fault events. The overall impedance of the 200 km hardware setup TL is 12 Ω. Considering the sensitivity, accuracy and reliability for the proposed algorithm and taking into account of fault resistance value of 10 with 1 Ω lead wire resistance, the threshold value is set to 23 Ω to verify more 900 recorded fault events. For different hardware setup or in real-time system, heuristic fault data of voltage and current signal are required for best tuning and setting of proposed algorithm. Fig. 13 shows the recorded waveform from real-time data recorder for A–g fault at 30 km TL from sending end generator with mid-point STATCOM controller for 0.1 Ω fault resistance. Fig. 13Open in figure viewerPowerPoint Real-time data recorder waveforms for A–g fault at 30 km with mid-point STATCOM controller for 0.1 Ω fault resistance Internal A–g fault at 30 km from sending end generator of line in hardware setup recorded results is shown in Fig. 14 with mid-point connected STATCOM. As this fault event is recorded in real-time digital data recorder, saved sampled data for the events are retrieved for algorithm validation. Fig. 14 (i) shows voltage waveform of phase A at sending end bus with estimated phasor magnitude by recursive DFT at 1 kHz sampling frequency and current waveform of phase A with estimated phasor magnitude. Fig. 14 (ii) shows the proposed per phase DIPR algorithm calculated ratios with per phase trip decisions. As observed from Fig. 14 (ii), fault was occurred at 0.36 s and trip decision is issued within half cycle as ratio of phase A is less than set threshold value. Fig 15 (i) shows recorded result for line-to-line fault at 130 km with voltage and current waveform of phases A and B at sending end generator with its estimated phasor magnitudes. Fig. 15 (ii) shows proposed DIPR algorithm calculated per phase ratios and trip decisions. Fig. 15 it is observed that fault is created at 0.26 s and trip decisions for both phases are issued within half cycle. Due to limited number of channels in the real-time data recorder, three-phase fault types are not verified. From rigorous case studies of >1000 cases of recorded fault events it was observed that the proposed algorithm performed accurately in per phase fault detection. The fault location algorithm and external fault cases are not verified due to hardware limitation but analytically and in simulation results DIPR algorithm performs superiorly. The recorded hardware setup fault events and presented simulation results prove the robustness and applicability of proposed algorithm for industrial use and its application in real-time system. Fig. 14Open in figure viewerPowerPoint Hardware setup recorded results for A–g fault at 30 km with 0.1 Ω fault resistance (i) (a) Voltage waveform of phase A (b) Estimated phasor (c) Current waveform of phase A (d) Estimated phasor, (ii) (a) DIPR ratio of phase A (b)Trip decision of phase A (c) DIPR ratio of phase B (d) Trip decision of phase B Fig. 15Open in figure viewerPowerPoint Hardware setup recorded results for AB fault at 130 km with 0.1 Ω fault resistance (i) (a) Voltage waveform (b) Estimated phasor (c) Current waveform (d) Estimated phasor, (ii) (a) DIPR ratio of phase A (b) Trip decision of phase A (c) DIPR ratio of phase B (d) Trip decision of phase B The proposed per phase DIPR ratio-based pilot relaying scheme is accurate and has no effect of STATCOM compensation level, installation point and its dynamic in comparison with the one given in [7–9]. The proposed scheme is tested with hardware results, and results prove the superiority of the proposed scheme over the other schemes. In comparison with that in [14], this scheme has fixed threshold setting, even STATCOM is active or inactive. The fixed threshold setting makes proposed relaying scheme simpler in comparison to other conventional schemes [10, 12]. Threshold setting can be calculated for any other transmission system using formula given in (15). In comparison with [7–9], the proposed relaying algorithm detects faults with high fault resistance and gives accurate detection of faulty phase. The computation burden is less when compared with other scheme in [14]. 6 Conclusion A per phase DIPR-based novel pilot relaying scheme for mid-point STATCOM compensated TL is proposed in this work. Mathematical analysis and simulation results show that the per phase DIPR ratio reflects capacitive impedance of TL in the presence of STATCOM at mid-point under healthy condition or during external fault condition. The per phase DIPR ratio value is >500 Ω for capacitive and >1400 Ω for inductive compensation. Whereas, the per phase DIPR ratio gives value equal to equivalent system and TL impedance value for all the internal faults with compensation and its value is always <350 Ω. Considering the abovementioned differences in the per phase DIPR ratio values, internal or external faults can be classified and detected accurately. Proposed scheme gives correct fault phase detection and selection ability in the presence of STATCOM compensation. The DIPR scheme is not affected by capacitive charging current, STATCOM operation dynamics, fault inception angle and fault distance which is main highlight of this scheme. The performance of proposed scheme is verified and evaluated for recorded fault events in hardware setup of two-machine system with mid-point STATCOM controller in offline mode using MATLAB. DIPR scheme works on per phase mode with the requirement of GPS time stamped both end measured data of corresponding phase. The detection time of proposed scheme is well within one cycle and can be brought to a less value than half cycle by sacrificing relay reliability. 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