Full soft‐switching high step‐up DC–DC converter based on active resonant cell
2017; Institution of Engineering and Technology; Volume: 10; Issue: 13 Linguagem: Inglês
10.1049/iet-pel.2016.1006
ISSN1755-4543
AutoresHadi Trazamni, Ebrahim Babaei, Mehran Sabahi,
Tópico(s)Multilevel Inverters and Converters
ResumoIET Power ElectronicsVolume 10, Issue 13 p. 1729-1739 Research ArticleFree Access Full soft-switching high step-up DC–DC converter based on active resonant cell Hadi Trazamni, Corresponding Author Hadi Trazamni hadi_tarzamni@yahoo.com Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorEbrahim Babaei, Ebrahim Babaei Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorMehran Sabahi, Mehran Sabahi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this author Hadi Trazamni, Corresponding Author Hadi Trazamni hadi_tarzamni@yahoo.com Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorEbrahim Babaei, Ebrahim Babaei Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorMehran Sabahi, Mehran Sabahi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this author First published: 08 August 2017 https://doi.org/10.1049/iet-pel.2016.1006Citations: 15AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract In this paper, a new full soft switching high step-up DC–DC boost converter is proposed. To achieve high voltage gain, a N-level voltage multiplier cell (VMC), and to achieve soft switching, a simple auxiliary resonant cell is implemented on a conventional pulse width modulation boost converter. All semiconductor devices are switched under soft switching conditions, which decrease the switching losses significantly. These soft switching conditions consist of zero voltage and zero current switching (ZVZCS) condition for both main and auxiliary switches, ZVZCS for auxiliary cell diode and zero current switching for all output VMC diodes. To control the output voltage in this converter, two degrees of freedom, consisting of the main switch duty cycle and output VMC level (N), are available. These degrees of freedom lead the converter to operate in a wide output voltage range and have maximum power point tracking implementation or output voltage regulation capabilities. In this paper, operational modes analysis, design procedure, application discussion, soft switching and power efficiency evaluations and simulation results are presented. Finally, experimental results with input voltage of 32 V, output power of 80 W and switching frequency of 20 kHz are given to prove the accuracy of theoretical analysis. 1 Introduction Nowadays working on power conditioning systems (PCS)s of renewable energy generators have great prominence, while the world's power demand is increasing [1, 2]. These PCSs need a DC–DC converter both to raise and regulate the output voltage in different applications [3]. In this case, high step-up DC–DC converters have special importance [4]. In [5], a cascaded DC–DC boost converter is used to achieve high-voltage gain. However, it suffers from hard switching and power losses. In [6], high-voltage gain is obtained by using coupled inductors. The problems with coupled inductors, however, are complicated design procedure of their characteristics and again power losses. In [7], a multi-winding coupled inductor and a voltage doubler are employed to generate high-output voltage. Although the voltage across the active switch is clamped to reduce the conducting losses and the energy of the leakage inductor is recycled, this converter suffers from switching losses, freewheeling currents and high number of active and passive components in comparison with generated output voltage level. In [8], high-voltage gain is achieved by interleaving DC–DC converters. In spite of current stress reduction on the switches, the duty cycle range of the switches is restricted in order to have less input current ripples. In [9], an interleaved high step-up DC–DC converter using coupled inductors and active clamp circuit is presented, where the coupled inductors in this topology are bulky. In [10], another interleaved DC–DC converter is introduced, where the current sharing of distributing equal currents in parallel DC–DC converters is sophisticated. In [11-13], isolated topologies are presented. In [11], in spite of low switch voltage stress, its transformer increases the size, cost and complexity of the whole converter. In [12], a pulse-width modulated (PWM) and phase-shifted interleaved DC–DC converter using quadrupler rectifier and voltage doubler is presented, where the high number of the components makes it impractical in industrial applications. In [13], high-output voltage is achieved within an isolated DC–DC converter, where high turning ratio of its transformer imposes high current and voltage stresses on the primary and secondary side semiconductor devices, respectively. Hence, non-isolated topologies could be appropriate choices of high step-up DC–DC converters [14, 15]. On the other hand, DC–DC converters have proper operation when their semiconductors are switched under soft-switching techniques to reduce power losses. In [16], a zero current switching (ZCS) technique is presented, where the resonant elements are bulky, causing the presented technique is less practical. In [17], a zero voltage switching (ZVS) topology is presented, where full soft switching is not accomplished, yet. In [18, 19], ZVS is achieved by an active clamp, where high current stress, reduced boost capacity and requiring a large high frequency capacitor for effective clamping are some of its obstacles. In [20, 21], zero voltage and ZCS (ZVZCS) techniques are employed to reduce switching losses, where an auxiliary switch [20], or a passive circuit [21] are used, both on the topologies’ secondary side, to apply ZVZCS techniques. The problem in these topologies is the circulating currents in freewheeling modes, which increases the conduction losses. There are other soft-switching techniques that use active auxiliary circuits consisting of active switches and passive components. For example, in [22], one of these techniques is used to help the main switches turn off softly. However, the auxiliary circuit with two active switches makes the total cost of the converter high and control circuits more sophisticated. In this paper, a new soft-switching high step-up DC–DC converter with a wide output voltage regulation according to its applications is proposed. It employs an auxiliary cell to help the semiconductor devices operate under full soft-switching conditions, where both main and auxiliary cells are turned on and off under ZVZCS. Furthermore, the diodes, including auxiliary and output voltage multiplier cell (VMC) diodes, switch under soft-switching conditions. The output voltage can be regulated both by the main switch duty cycle and the VMC level (N), which helps the converter operate in a wide output voltage range in different industrial application. In addition, these two degrees of freedom make the proposed converter have maximum power point tracking (MPPT) capability. Then, all soft switching, high-voltage gain, MPPT and output voltage regulation capabilities with two degrees of freedom make the proposed converter suitable in renewable energy systems, especially in photovoltaic (PV) applications. This paper presents operational modes analysis, power efficiency evaluations and experimental prototype results to verify its operation accuracy. 2 Proposed converter The proposed converter is presented in Fig. 1a, where an auxiliary resonant cell (, , , and ) is employed in a conventional PWM boost converter ( and ) to provide full soft-switching conditions for semiconductors. It should be noted that in this figure is an external capacitor. In addition, a VMC is used to improve the voltage gain of the converter. To simplify the operational modes analysis, the following assumptions are made: (i) All components are ideal. (ii) The inductor is considered large enough to be assumed with constant current, . (iii) The input voltage, , is constant. (iv) The output filter capacitor, , is large enough, so the output voltage, , can be considered constant during a switching period, T. Fig. 1Open in figure viewerPowerPoint Proposed soft-switching high step-up converter (a) Proposed N level converter, (b) Simplified equivalent topology of proposed converter for soft-switching analysis 2.1 VMC operation An N-level VMC, which requires diodes and capacitors, is shown in Fig. 2a. The operation of this cell is divided into two separated intervals. The first interval occurs when the main switch (or its body diode) of boost converter is on. In this interval, the even-numbered capacitors are charged by the voltages across odd-numbered capacitors. This operation is depicted in Figs. 2b and c. The other interval occurs when this switch is off. In the second interval, the odd-numbered capacitors are charged by main input inductor. The charging flow path in this mode is presented in Figs. 3d and e. These figures can be generalised to the th capacitor. So, by charging and discharging the odd and even-numbered VMC capacitors consecutively, the output voltage is increased to higher levels. Fig. 2Open in figure viewerPowerPoint N-level VMC (a) Topology, (b), (c) Current path in first interval, (d), (e) Current path in second interval Fig. 3Open in figure viewerPowerPoint Operational modes of proposed converter from soft-switching point of view (a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5, (f) Mode 6, (g) Mode 7, (h) Mode 8, (i) Mode 9, (j) Mode 10, (k) Mode 11, (l) Mode 12, (m) Mode 13, (n) Mode 14 The N parameter, which demonstrates the output VMC level, is one of the degrees of freedom besides the duty cycle of main switch () in the proposed converter. This parameter can be selected to appropriate number in the design procedure, in order to reach the desired output voltage gain. In addition to higher output voltage gains, the output voltage regulation range is increased by increasing N-level, since it is the coefficient of output voltage gain equation with direct relationship [14]. All equations about the VMC operation with hard switching boost converter are available in [14]. The aforementioned cell is used in [14, 23, 24] with PWM boost converters and in [25] with an interleaved conventional PWM boost converter to achieve high-voltage gain, where soft switching is ignored in these converters. 2.2 Soft-switching fundamentals As shown in Fig. 1b, in order to simplify the soft-switching analysis of the proposed converter, the VMC is modelled by an equivalent circuit including a diode () and a capacitor (). This figure illustrates the proposed converter with . All soft-switching fundamentals, which are analysed in Fig. 1b, are accepted in the main proposed converter of Fig. 1a. In order to operate under soft-switching conditions, the proposed converter contains 14 modes. The current flow path in each mode is shown in Figs. 3a–n. These modes are analysed as follows: Mode 1 (): In this mode, the switches of and are off, and the input power is transferred directly to the output load through output equivalent diode, . Mode 1 is similar to the conventional boost converter when its main switch is off. During this mode, the resonant capacitors voltages, and , are equal to the constant values of and , respectively. Mode 2 (): At , the switch is turned on under ZVZCS, since the resonant inductor, , is in the current path flow of this switch. In this mode, the inductor and capacitor begin to resonate causing inductor current and capacitor voltage to increase as follows: (1) (2)where and are resonant angular frequency and characteristic impedance of resonance between and , respectively, and are determined as (3) Moreover, output current, , decreases as follows: (4) Mode 2 ends when reaches . The time interval of this mode is equal to (5)Mode 3 (): At , diode turns on under ZVZCS. During this mode, the voltage across inductor is equal to the constant value of , which charges it linearly as follows: (6)where is equal to (7) In this mode, the output current, , decreases linearly as follows: (8) Mode 3 ends when reaches . The time interval of this mode is equal to (9)Mode 4 (): At , diode turns off under ZCS and inductor and capacitor start to resonate. This resonance causes to increase and to decrease as follows: (10) (11)where and are resonant angular frequency and characteristic impedance of resonance between and , respectively, and are determined as (12) So, the diode voltage can be concluded as (13) Mode 4 ends when reaches zero. The time interval of this mode is equal to (14)Mode 5 (): At , the body diode of switch, , turns on under ZVZCS. During this mode, the inductor current decreases linearly as follows: (15) Mode 5 ends when reaches . The time interval of this mode is equal to (16)Mode 6 (): At , the diode turns off and switch is turned on, both under ZVZCS. To guarantee the soft-switching condition of switch, its turn on gate signal should be applied before , while diode is still conducting. The inductor current () continues to decrease in this mode as follows: (17) Mode 6 ends when the inductor current () reaches zero. The time interval of this mode is equal to (18)Mode 7 (): At , diode turns off, diode turns on and switch is turned off, all under ZVZCS. During this mode, inductor and capacitor resonate for half of a resonant period, which reverses the polarity of as follows: (19) (20) Mode 7 ends when the inductor current () reaches zero. The time interval of this mode is equal to (21)Mode 8 (): At , diode turns off under ZCZVS. This mode is similar to the conventional boost converter when its main switch is on, in which the input current flows through switch. The time interval of this mode is dependent on the on-time of switch. Mode 9 (): At , switch is turned on under ZVZCS. During this mode, inductor and capacitor resonate, causing and increase as follows: (22) (23) Mode 9 ends when reaches which causes decrease to zero. The time interval of this mode is equal to (24)Mode 10 (): At , diode turns on under ZVZCS and switch can be turned off under ZVZCS. During this mode, the resonance between and leads to positive voltage. The inductor current () and capacitor voltage () can be expressed as follows: (25) (26) Mode 10 ends when reaches again. The time interval of this mode is equal to (27)Mode 11 (): At , diode turns off under ZVZCS. During this mode, inductor resonates with and capacitors in which decreases and the and increase as follows: (28) (29) (30)where and are resonant angular frequency and characteristic impedance of resonance between , and , respectively, and are determined as (31)then is equal to (32) Mode 11 ends when reaches . The time interval of this mode is equal to (33)Mode 12 (): At , diode turns on under ZVZCS. In this mode, is equal to , decreases and increases due to the resonance between and . These equations are equal to (34) (35) Mode 12 ends when reaches zero. The time interval of this mode is equal to (36)where (37)Mode 13 (): At , diode turns on under ZVZCS, due to the existence of inductor in the current flow path of this diode. Moreover, diode turns off under ZVZCS and switch can be turned off under ZVZCS. In this mode, resonates with the capacitors of and . The equations can be expressed as (38) (39) (40) Mode 13 ends when reaches zero again. The time interval of this mode is equal to (41)Mode 14 (): At , diode turns off under ZVZCS. During this mode, is increased linearly by the input current, , flows through it. Its equation is equal to (42) Mode 14 ends when reaches . At , one switching period ends and another switching period begins with turning on diode under ZVZCS. The time interval of this mode is equal to (43) According to the whole voltage and current equations of components in this section, the steady-state key waveforms are presented in Fig. 4. As shown in this figure, the switch is operated under a conventional PWM control and switch is only activated in switching transition times, which prevents high conduction loss of switch. Fig. 4Open in figure viewerPowerPoint Steady-state key waveforms 3 Comparison A comparative view of the soft-switching conditions along with the component numbers of the proposed converter and other previous works is tabulated in Table 1. In this table, the dash marks indicate the elements, which are not existed in each topology. This table shows the soft-switching capability of the proposed converter in comparison with other similar soft-switching topologies. As indicated in Table 1, all active and passive semiconductor devices of the proposed converter, including main and auxiliary ones are commutated under soft-switching conditions at both turn on and turn off transitions, where in [26-29], at least one semiconductor device is hard switched. In [30], the near soft-switching conditions nominated as, zero voltage transition (ZVT) and zero current transition (ZCT), occur in all components, but complete true soft switching is not provided. In [31], all semiconductors are soft switched, however, it employs one more inductor, which makes that topology bulky in size and expensive in cost. In [32], soft switching is accomplished with a flyback snubber by using more diodes and one transformer, therefore efficiency is reduced. Table 1. Comparison of converters’ soft-switching features Ref. Components On Off On Off On Off On Off On Off On Off L C this paper ZVS ZVS ZVS ZVS ZVS ZVS ZVS ZCS — — — — 2 3 ZCS ZCS ZCS ZCS ZCS ZCS ZCS [26] Hard ZCT ZCS Hard ZCS ZCS ZCS Hard — — — — 2 2 [27] ZVS Hard ZVS Hard Hard ZCS Hard ZCS — — — — 2 3 [28] ZVS ZVS ZCS ZVS ZVS ZCS ZVS ZCS — — — — 2 3 [29] ZVS Hard ZVS ZVS — — ZCS ZCS — — — — 3 2 [30] ZVT ZCT ZCS ZCT — — ZVS ZVS — — — — 2 3 ZCS [31] ZVS ZVS ZCS ZCS ZVS ZCS ZVS ZCS — — — — 3 3 ZCS [32] ZVT ZCS ZVT ZCS ZVS ZCS ZVS ZCS ZVS ZCS ZVS ZCS 3 2 4 Design procedure In order to control and time intervals, there are some commutation conditions in the proposed converter to guarantee the soft switching of active semiconductors in simplified converter of Fig. 1b. By using (15)–(18), to turn on switch at the end of mode 5 and turn off switch at the end of mode 6 both under ZVZCS, an inequality should be considered as follows: (44) Also, by using (22)–(24), to turn off switch at the end of mode 9 under ZVZCS, an inequality should be satisfied as follows: (45) Equation (45) can be rewritten as (46)where and are the maximum value of input current and the minimum value of input voltage, respectively. In the following, a complete design procedure including a numerical example to determine element values is given, which guarantees the ZVZCS condition of the proposed DC–DC boost converter. The input values are assumed to satisfy output voltage regulation as follows: utput power: 80 W; utput voltage:218 V; input voltage: 32 V (); input inductor ripple: ; approximate efficiency: ; utput VMC level: N = 3. With the output power and approximate efficiency values available above, the input power and maximum input current are calculated as (47) (48) In order to control the rate of the inductor and therefore, to minimise the reverse recovery time of the output diodes, inductor is calculated, with the assumed value of for , as follows: (49) With the magnitude of , the magnitude of is selected as , which is the standard range of capacitors in experimental prototype and satisfies the soft switching of switch at the end of mode 9. From input and output voltages available, the DC voltage gain of the designed high step-up DC–DC converter is concluded as (50)where the defined DC voltage gain satisfies (44). Here capacitor is assumed as equal as . As it is obvious, the switching period must be greater than the summation of resonant transition times which are given in (5), (9), (14), (16), (18), (24), (27), (33), (36), (41) and (43). In this paper, the sum of the resonant transition times is assumed as equal as the 16% of the switching period, T. So, the maximum value of the switching frequency with the designed values is as follows: (51) In this design, the switching frequency (f) is assumed as 20 kHz. The value of the output VMC capacitors are not related to the basic soft-switching operation of the converter and it only affects the transient start up time. In this paper, these capacitors are chosen as . 5 Application discussion In this section, the two capabilities of the proposed converter are discussed, which help it be applicable in renewable energy systems. In these capabilities, the duty cycle of main switch (D) is utilised as a degree of freedom. 5.1 Output voltage regulation This capability is essential, where a fixed voltage must be given to the DC link or load at the output terminal. The controlling block diagram of this capability is presented in Fig. 5a. As shown in this figure, first, fixed must be defined to the output voltage, in which it is regulated. is compared with measured real time and their subtraction is equal to the voltage error, which is applied to the controller. Considering the voltage error sign and magnitude, the controller calculates appropriate value for D, in order to apply to . Then, since the converter is designed in soft-switching operation and , , and time durations are determined, switch gate pulses are synchronised with and to turn on and off at accurate times of , , and , respectively, to satisfy soft-switching conditions. This synchronisation procedure last for some switching periods in voltage regulation to achieve approximately at . Fig. 5Open in figure viewerPowerPoint Applications of proposed converter (a) Output voltage regulation controlling block diagram, (b) P&O algorithm diagram, (c) versus of a PV panel 5.2 Maximum power point tracking In order to save energy and utilise the PV panel more efficiently, MPPT with the power conditioning system, connected to PV panel, is one of the practical approaches. This capability is accessible in the proposed converter by controlling D, which can change the seen impedance of the converter from PV panel. In this paper, the conventional perturbation and observation (P&O) algorithm is used to reach maximum power point (MPP). P&O algorithm block diagram and versus of a PV panel are shown in Figs. 5b and c, respectively. In this algorithm, after applying a perturbation, the difference between measured in two consecutive times of k and results in , in which k is the counter parameter of the algorithm loop. Furthermore, by calculating with the similar procedure of between k and , can be concluded. As it is clear in Fig. 5c, must be increased and decreased in and , respectively, to reach MPP. In the proposed converter, in order to increase and decrease , D must be decreased and increased, respectively. Also, in the region of , the ratio of has positive sign with any perturbations, which is a negative value in . So, by using the sign of , the region of operating point is detected and by using this sign, appropriate changes are applied in D to increase or decrease and reach MPP. 6 Simulation and experimental results In order to validate the theoretical analysis, a simulation in PSCAD/EMTDC software is done and an 80 W experimental prototype with parameter values designed in the preceding section is developed. In the prototype, which is shown in Fig. 6, IRFP470 and MUR1560 are used as switches and diodes, respectively. These switches and diodes are used to have a wide power range in the experimental prototype. In addition, an ARM (LPC1768) microcontroller is used as a switch gate pulse generator. Fig. 6Open in figure viewerPowerPoint Experimental setup (a) Drivers power supply transformer, (b) Prototype, (c) Microcontroller, (d) current test resistance, (e) on scope, (f) Output load The non-ideal simulation and experimental results are shown in Fig. 7, which coincide the analysed waveforms. As highlighted in this figure, soft-switching operation of the proposed converter is clear in current and voltage waveforms. It must be mentioned that, Figs. 7a–j give in output voltage regulation condition and Fig. 7k gives to verify MTTP. In Figs. 7a and g, the control pulses applied to the gates of the switches of experimental and simulation results are presented. In Figs. 7b and i, the current of switch with its anti-parallel body diode is shown, where the negative current passes through the diode. In mode 8, the current increases linearly since the non-ideal situations of experimental results, which was assumed as constant value of in theoretical analysis. In Figs. 7c and j, the operation of auxiliary resonant cell is shown by the sinusoidal and linear waveforms of , which guarantees the ZCS of switch. In Fig. 7d, current and voltage of one of the output VMC diodes are shown, where soft-switching conditions are clear and this can be generalised to other output VMC diodes. Fig. 7Open in figure viewerPowerPoint Continued Fig. 7Open in figure viewerPowerPoint Simulation and experimental results with (a) and , (b) and , (c) and , (d) and , (e) , (f) and , (g) and , (h) , (i) and , (j) and , (k) MPPT test result The voltage across capacitor is shown in Figs. 7e and h, where it operates with sinusoidal waveforms between constant voltages of and , as verified in theoretical analysis. Finally, in Fig. 7f, the voltage boosting capability of the proposed converter is shown by input and output voltage levels, as which was determined in design procedure. Moreover, in order to verify the MPPT capability of the proposed converter, it is tested under MPPT conditions with P&O algorithm (see Fig. 5b) and the result is given in Fig. 7k. As presented in this figure, the proposed converter can operate on the plot, in a way to achieve MPP. In the tested conditions, and are resulted for MPP. To analyse power loss and then the power efficiency of the proposed converter, its power loss is calculated as (52)where the power losses of passive elements and conduction losses of the semiconductors (cond) are considered in this equation. The following equation is always considered in power efficiency analysis (53) The power efficiency of the proposed converter in different output powers is shown in Fig. 8a, which is compared with three other similar literature, using VMC cells [14, 24, 25]. In this figure, the power efficiency diagram of [14, 24] is shown in limited output power ranges, which were exactly given in original papers. The maximum efficiency of the proposed converter is 95.09%, which is achieved in output power of 193 W. As compared in Fig. 8a, the proposed converter has higher efficiency in comparison with other three converters, because, unlike [14, 24, 25], the proposed converter employs soft-switching techniques. For instance, in [25], by using both interleaving technique and VMCs the output power and the efficiency is improved, however, soft-switching operation of the proposed converter results in higher power efficiency. Moreover, in order to analyse the ratio of components’ power losses to the total power loss in different output powers, the percentage power loss plot of Fig. 8b is presented. As shown in this figure, the output VMC diodes and capacitors and have the highest power losses in comparison with other components. Note that, Fig. 8b results from the converter operation with output VMC level of , so, diodes and capacitors are employed in the output VMC. Fig. 8Open in figure viewerPowerPoint Operational plots of the proposed converter (a) Power efficiency against output power, (b) Percentage power loss of components versus output power, (c) Power efficiency against output power with different N values, (d) Voltage gain of the proposed converter with different D and N values, (e) Voltage gain comparison of designed and full load conditions As it is clear, by considering constant values for and R, increasing N causes the output voltage, output power, input current, component number and power losses increase. Hence, to analyse the effect of N on the power efficiency, Fig. 8c is presented, in which the power efficiency changes versus output power in VMC levels of , and are depicted. As shown in this figure, the power efficiency plot of the proposed converter is improved in in comparison with . However, in , the efficiency is decreased, since higher power losses. As calculated in [14], voltage gain of the hard switching boost converter along with a VMC is equal to (54)where D can be used as the second degree of the freedom to regulate output voltage or MPPT in the proposed converter. Since in the proposed soft-switching converter has some sinusoidal modes, operating in auxiliary resonant cell, it has less direct power transfer to the load than hard switching one. Therefore, its voltage gain is less than (54). However, this deficiency in voltage gain is little, because of the short time the resonant cell is activated. The voltage gain of the proposed converter with different D and N values is shown in Fig. 8d. Also, in order to compare the efficiency plot of designed load power for and full load operation, Fig. 8e is given. As shown in this figure, in lower values of D, full load efficiency plot is a bit higher than the designed load power efficiency. This is caused by the effect of output load on the voltage gain, which is small. However, power loss increase in full load for higher values of D, causes its efficiency reduce. For instance, in , the efficiency of designed load power is approximately 5% higher than the full load one. 7 Conclusion In this paper, a full soft-switching high step-up DC–DC converter is proposed. It contains an auxiliary resonant cell and a VMC cell to achieve soft switching for semiconductor devices and high-voltage gain, respectively. The resonant cell provides ZVZCS condition for main and auxiliary switches. In addition, the auxiliary diode and output diodes operate under ZVZCS and ZCS, respectively. The proposed converter operates with no freewheeling current, which increases the converter efficiency. The output voltage of the proposed converter can be controlled both by the duty cycle of main switch and the VMC level, which is very suitable in PCSs of renewable energy generators, more common in PV systems. By using appropriate PWM controls, MPPT can be applied in this topology. Furthermore, no transformers are used in the proposed topology. This feature besides the abovementioned characteristics leads in higher power efficiencies, while achieving high-voltage gains. In this paper, the operation modes analysis, design procedure, application discussion and power efficiency evaluations are presented. Moreover, the soft-switching capability of the proposed converter is tabulated to compare with other similar previous works. Furthermore, an experimental prototype with input voltage of 32 V, output power of 80 W and switching frequency of 20 kHz with VMC level of is developed to validate the theoretical analysis. 8 References 1Wu H., Xu P., and Hu H.: ‘Multiport converters based on integration of full-bridge and bidirectional DC-DC topologies for renewable generation systems’, IEEE Trans. Ind. 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