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A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

2017; Institute of Electrical and Electronics Engineers; Volume: 52; Issue: 9 Linguagem: Inglês

10.1109/jssc.2017.2718665

1558-173X

Hyeon‐June Kim, Sun-Il Hwang, Jae-Hyun Chung, Jong-Ho Park, Seung‐Tak Ryu,

Image Processing Techniques and Applications

This paper presents a CMOS image sensor (CIS) that extracts a multi-level edge image as well as a human-friendly normal image in a real time from conventional pixels for machine-vision applications, utilizing a proposed speed/power efficient dual-mode successive-approximation register analog-todigital converter (SAR ADC). The proposed readout scheme operates in two modes, fine step SAR (FS-SAR) mode and coarsestep single-slope (CS-SS) mode, depending on the difference (A) between a chosen pixel and the previous pixel. If a chosen pixel is at a boundary of an object with a large A from the previous pixel, the readout ADC works in the CS-SS mode to readout the edge strength (ES), while the FS-SAR mode is applied for other pixels. By displaying the ES, a multi-level edge image can be obtained in a real time along with a normal image with no hardware/time overhead. By saving the MSBs conversion cycles regardless of A, the proposed dual-mode readout scheme enhances the readout speed and reduces power consumption. A prototype QQVGA CIS with 10-bit SAR ADCs was fabricated in a 0.18-μm 1P4M CMOS image sensor process with a 4.9-μm pixel pitch. With a maximum pixel rate of 61.4 Mp/s, the prototype demonstrated figure of merits of 70 pJ/pixel/frame, 0.35 e̅ nJ, and 0.34 e̅ pJ/step.