Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
2017; Linguagem: Inglês
10.23919/vlsit.2017.7998183
AutoresN. Loubet, Terence B. Hook, P. Montanini, Chun Wing Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, Xiren Miao, J. Wang, Anthony Young, R. Chao, Mingu Kang, Zhe Liu, S. Fan, Bassem Hamieh, Stuart Sieg, Yann Mignot, Wenyu Xu, Soon‐Cheon Seo, J. Yoo, Shinichi Mochizuki, M. Sankarapandian, Oh-Hoon Kwon, Adra Carr, Andrew Greene, Y. Park, Julien Frougier, Rohit Galatage, R. Bao, Jeffrey C. Shearer, Rena M. Conti, Hyo‐Jong Song, Dae‐Young Lee, Dexin Kong, Yang Xu, Abraham Arceo, Zhichun Bi, P. Xu, Raja Muthinti, J. Li, Robert Wong, D.E. Brown, Phil Oldiges, Robert R. Robison, John Arnold, Nelson Felix, Spyridon Skordas, John G. Gaudiello, T. Standaert, H. Jagannathan, Dan Corliss, M.-H. Na, Andreas Knorr, Tian‐Li Wu, Divya Gupta, S. Lian, R. Divakaruni, T. R. Gow, Catherine B. Labelle, S. Lee, Vamsi Paruchuri, H. Bu, Mukesh Khare,
Tópico(s)Ferroelectric and Negative Capacitance Devices
ResumoIn this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.
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