Low‐loss BiCMOS spoof surface plasmon polariton transmission line in sub‐THz regime
2017; Institution of Engineering and Technology; Volume: 12; Issue: 2 Linguagem: Inglês
10.1049/iet-map.2017.0021
ISSN1751-8733
AutoresZihang Qi, Xiuping Li, Hua Zhu,
Tópico(s)Photonic Crystals and Applications
ResumoIET Microwaves, Antennas & PropagationVolume 12, Issue 2 p. 254-258 Research ArticleFree Access Low-loss BiCMOS spoof surface plasmon polariton transmission line in sub-THz regime Zihang Qi, Zihang Qi School of Electric Engineering, Beijing University of Posts and Communications, No 10, Xitucheng Road, Haidian District, Beijing, People's Republic of China Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, 100876 Beijing, People's Republic of ChinaSearch for more papers by this authorXiuping Li, Corresponding Author Xiuping Li xpli@bupt.edu.cn School of Electric Engineering, Beijing University of Posts and Communications, No 10, Xitucheng Road, Haidian District, Beijing, People's Republic of China Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, 100876 Beijing, People's Republic of ChinaSearch for more papers by this authorHua Zhu, Hua Zhu School of Electric Engineering, Beijing University of Posts and Communications, No 10, Xitucheng Road, Haidian District, Beijing, People's Republic of China Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, 100876 Beijing, People's Republic of ChinaSearch for more papers by this author Zihang Qi, Zihang Qi School of Electric Engineering, Beijing University of Posts and Communications, No 10, Xitucheng Road, Haidian District, Beijing, People's Republic of China Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, 100876 Beijing, People's Republic of ChinaSearch for more papers by this authorXiuping Li, Corresponding Author Xiuping Li xpli@bupt.edu.cn School of Electric Engineering, Beijing University of Posts and Communications, No 10, Xitucheng Road, Haidian District, Beijing, People's Republic of China Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, 100876 Beijing, People's Republic of ChinaSearch for more papers by this authorHua Zhu, Hua Zhu School of Electric Engineering, Beijing University of Posts and Communications, No 10, Xitucheng Road, Haidian District, Beijing, People's Republic of China Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, 100876 Beijing, People's Republic of ChinaSearch for more papers by this author First published: 04 January 2018 https://doi.org/10.1049/iet-map.2017.0021Citations: 10AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract This study presents an on-chip spoof surface plasmonic polariton transmission line (sSPP-TL) in the sub-THz regime. The proposed sSPP-TL is designed and fabricated in the standard BiCMOS process. To eliminate the influence of a high index silicon substrate, a special underlying ground shielding plane is introduced. A mode converter is designed with both impedance and momentum matching in order to achieve efficient conversion from grounded coplanar waveguide to sSPP-TL. Electromagnetic (EM) simulated and measured results show good conversion efficiency from quasi-transverse EM to sSPP mode (measured input reflection coefficient is below −18.5 dB). More importantly, a low propagation loss profile (average measured insertion loss is 1.54 dB/mm) is observed in the broadband frequency range in sub-THz (140–325 GHz). The demonstrated sSPP-TL has shown great potential for on-chip sub-THz communication in the standard silicon process. 1 Introduction Nowadays, the requirement of wideband on-chip communication between microprocessor cores and memory sharply grows in high speed computing systems. Future microprocessors may encounter communication congestion and most of the energy will be spent on ''talking' instead of computing. A 20 Gbps or higher bandwidth is needed to build up a network on-chip, and its energy consumption is limited to 0.1 pJ/bit/mm [[1]]. Scaled chip wiring (interconnect) suffers from increased resistance due to a decrease in the conductor cross-sectional area and may also suffer from increased capacitance if the metal height is not reduced with conductor spacing. Radiofrequency interconnect (RF-I) is one solution owing to its lower latency and larger bandwidth [[2]]. In contrast to traditional voltage signalling in the baseband, RF-I basically transmits a high-frequency electromagnetic (EM) wave along the transmission line (TL). Compared with optical on-chip communication by using an optical I/O link, the RF-I transmitter/receiver blocks and channels can all be built in the same silicon process with carrier frequency scaled up to the millimetre wave and sub-THz frequency regime. Recent works have demonstrated multi-channel RF-I to leverage much larger bandwidth utilisation. However, the complementary metal oxide semiconductor (CMOS)/BiCMOS back end of line (BEOL) used in fine-pitch silicon interconnect for RF-I is highly field-delocalised at high frequency, resulting in large channel loss with narrow bandwidth at high frequency. Moreover, in order to fulfil a certain bit error rate requirement, the data rate will be ultimately limited by the low phase noise of an on-chip oscillator in THz. Surface plasmon polariton (SPP) is a highly localised surface wave that propagates along the interface between two materials and that has opposite electric permittivity in the real part. Recently, SPP has drawn great attention due to its huge potential applications in various areas [[3]]. Originally, SPP exists in optical regimes [[4], [5]]. Various structures that support spoof surface plasmon polariton (sSPP) modes have been reported in the microwave or terahertz regime [[6]–[11]], ever since J. Pendry proposed one perforated conducting surface that can propagate which is called sSPP in 2004 [[12]]. Among these reports, Stefan A. Maier firstly introduced periodically corrugated structures on metal wires in the terahertz regime. Importantly, the propagation characteristics of these sSPP-TLs can be controlled by the surface geometry, opening the way to applications in the microwave and THz regime [[9]]. T. J. Cui's research team firstly reported sSPP-TL and several other applications later on in the microwave regime [[13]–[17]]. The radiation of one sSPP-TL can also be easily modulated by regularly changing its corrugated structure. The modulated radiation can then be used in antenna design especially for the beam-steering purpose [[18]]. Z.N. Chen's research team gave the details of a theoretical model of the microwave slow-wave TL based on the sSPP mode [[8]], which will be a vital reference to the design of sSPP-TL in the microwave or THz regime. Mode conversion from transverse EM (TEM) or quasi-TEM wave to sSPP mode is an important issue in sSPP's application. Gradient structures, such as gradient groove depths and flaring ground plane, are often employed which can provide high conversion efficiency from both impedance and momentum aspects [[19], [20]]. However, in the standard CMOS process, it is impossible to fabricate these structures due to the constraint of the design rules. Particularly, CMOS integrated circuits with plasmonic technology could operate at a much faster speed than current electronics, while 100 times thinner than glass fibres [[21]]. H. Yu's research team firstly proposed the on-chip sub-THz sSPP-TL in CMOS in 2015 [[22]] and a new converter from the conventional line to sSPP-TL is shown in their recent report [[21]]. It has been proved that compared with conventional differential microstrip lines sSPP-TLs will reduce much crosstalk than microstrip lines [[23]]. This may greatly enhance the performance of the system if they are applied in modern integrated circuit design. These experiments bring a new prospect to the future's highly integrated and highly efficient on-chip communication system. In this study, the on-chip sSPP-TL with symmetric grooves is designed and fabricated in the standard silicon process, combined with a converter from the grounded coplanar waveguide (GCPW) to sSPP-TL. The structure and performance of the sSPP-TL are presented and discussed in detail. With carefully optimising the converter from GCPW to sSPP-TL, TEM mode can be transferred to sSPP mode smoothly. EM simulated and measured results show good conversion efficiency from quasi-TEM to sSPP mode. Furthermore, a low propagation loss profile is observed in the broadband frequency range in the sub-THz regime. 2 Planar sSPP-TL design The behaviour of the sub-THz sSPP-TL primarily depends on the geometry of the corrugations. It has been shown that by introducing a sub-wavelength corrugated structure onto both sides of the metal line periodically, the structures have behaviours very similar to plasmonic waves in the microwave or THz regime [[20], [24]]. The structure of the proposed on-chip sSPP-TL with design parameters is illustrated in Fig. 1a. The periodic pitch t is designed which is far less than the working wavelength (1 mm@300 GHz). The top aluminium layer (TM1, which is thick) is used for the periodic groove metal line, the lowest thin metal layer(M1) is used as an underlying shielding metal, in order to restrict E-field between the two conductors, which is different from the implementation on the board level. Without the ground layer, a large portion of energy will be absorbed by the lossy silicon substrate. The height between the TM1 layer and the M1 layer is . Fig. 1b shows the simplified metal and substrate configuration of the model. Actually, SiO2 is divided into seven layers with different relative permittivity around 4.0. Note that the SiO2 substrate is high above the TM1 layer in the model and the polyimide layer is added at the top layer to make it consistent with the actual structure. Ref. [[25]] reports the loss tangent of SiO2 has a linear relationship with a frequency change and becomes 0.0021 at 300 GHz. We set the loss tangent of SiO2 0.0021 at 300 GHz with one order dependency on the frequency to fit this relationship. Fig. 1Open in figure viewerPowerPoint Structure view with dimensions of the on-chip sSPP-TL (a) 3D structure view with dimensions of the on-chip sSPP-TL, (b) Simplified configuration of metal and substrate layers 2.1 Dispersion and field confinement One unit (illustration in Fig. 2, substrates and M1 layers are hidden) is simulated in commercial EM simulator CST Microwave Studio using an eigenmode calculator, to evaluate the dispersion property. Note that with symmetric grooves on both sides of the line, both symmetric mode (even mode) and asymmetric mode (odd mode) surface waves can be excited and propagated [[24]]. Fig. 3 shows the detailed field distributions of even and odd modes in four different phase states. Fig. 2Open in figure viewerPowerPoint Simulated even and odd mode dispersion curves with different groove depth h ranges from to (periodic pitch t, groove width a and line width w are fixed) Fig. 3Open in figure viewerPowerPoint field distribution comparison of the even mode and odd mode in four phase states Fig. 2 shows the simulated dispersion curves of the propagating sSPP both even and odd modes corresponding to various groove depths from to . As depicted in the figure, the asymptotic frequencies are bending away from the light curve . The asymptotic frequency decreases with deeper grooves while keeping the width of the centre line identical . This phenomenon demonstrates that deep grooves for high confinement while shallow grooves for loose confinement. When the groove depth decreases to zero sSPP-TL degenerates to the microstrip line. Additionally, we can also realise that there exists a momentum mismatch between quasi-TEM mode and sSPP mode, so an efficient converter is needed. Compared with the odd mode, the even mode has a much broader working frequency band below its asymptotic frequency, and also has a larger propagation constant at a fixed frequency, implying strong confinement of the SPP waves. In the following sections, we will only focus on the propagation of the even mode. By using the finite integration technique method in CST Microwave Studio, the generation of sSPP mode in the proposed sSPP-TL structure can be confirmed. For parametric analysis, Fig. 4a illustrates the simulated E-Field on the yoz-plane evaluated at the periodic groove metal strips with different groove depths h at 2 THz. The details of confinement can be further observed from E-field enhancement in the cross-sections perpendicular to the metal strips, as shown in Fig. 4b. Here, we draw a straight line across the grooves and calculate the component. The field obviously decays exponentially along the orthogonally lateral y-axial directions (they are symmetrical along the strip directions corresponding to their geometric symmetry), illustrating the typical feature of sSPP mode – the decay becomes stronger as h increases (the centre of the line is located at ). Fig. 4Open in figure viewerPowerPoint E-field confinement of the proposed sSPP-TL (a) E-field confinement at the yoz-plane at 2 THz ( and ), (b) The simulated component along the vertical cut at 2 THz for different groove depth h ranged from to (periodic pitch t and groove width a are fixed) 2.2 Bloch impedance of sSPP-TL In the design, Bloch impedance of the sSPP-TL is calculated to ensure the compatibility with GCPW. The Bloch impedance is the characteristic impedance of the TL periodically constructed by the sSPP unit cells [[8]]. The input impedance can be calculated by (1) The transmission parameters (A, B) can be transformed from the scattering parameters [[26]]. As demonstrated in Fig. 5, the impedance stays around for a wide range of frequencies when we chose sSPP-TL width and groove width . Fig. 5Open in figure viewerPowerPoint Bloch impedance of the proposed sSPP-TL According to the above design, the sSPP-TL main parameters are set as follows: periodic pitch , groove width , groove depth . 3 Mode conversion To exploit the high field confinement of the sSPP mode in microwave/THz circuits, a converter is needed to connect between conventional TL and sSPP-TL, which will bring a wider application and better compatibility of the proposed sSPP-TL structure. Aiming a highly efficient conversion, it is necessary to match the impedance, polarisation and momentum of the two parts. Based on the proposed design, the impedance of the sSPP-TL is designed at , so there is no more impedance matching needed. Owing to the constraints of plane metals' design rule in the standard silicon integrated circuit process, conventional high efficiency converter designs employing flaring ground plane [[20]] in board level at the microwave region cannot be duplicated in the on-chip scenario. In this design, a GCPW with bending ground plane is applied for mode conversion under the constraint of the design rule. Coplanar waveguide (CPW) to sSPP-TL and GCPW to sSPP-TL converters are considered in this study. Dimensions of the two types of converters are shown in Fig. 6.a and b. Both of them are designed with characteristic impedance. Converters are added to both ends of one sSPP-TL for simulation. From the comparison of simulation results in Fig. 6c, we can observe that CPW to sSPP-TL transition gives a big reflection. This may be due to a momentum mismatch. On the other hand, GCPW to sSPP-TL transition shows a low reflection which implies a good match. Fig. 6Open in figure viewerPowerPoint Reflection comparison of CPW to sSPP-TL and GCPW to sSPP-TL (a) Structure of CPW to sSPP-TL, (b) Structure of GCPW to sSPP-TL, (c) Reflection comparison of CPW to sSPP-TL and GCPW to sSPP-TL The GCPW line supports quasi-TEM modes, and these modes should be transformed to transverse magnetic (TM) polarised sSPP mode. Fig. 7b shows the component of the electrical field at four perpendicular planes in Fig. 7a at 2 THz. It can be observed that the component gradually increases along the converter from GCPW to sSPP-TL. At GCPW line is merely zero, and the becomes very strong at the sSPP line. These results clearly demonstrate a gradual transformation from quasi-TEM modes to TM modes. This can be further confirmed by the soy-plane view of the field component as shown in Fig. 7c. The colour scales from the great field strength (red and blue, indicating positive and negative phases, respectively) to the lowest (green), illustrating that sSPP mode travels from left to right with a low attenuation. Fig. 7Open in figure viewerPowerPoint Mode conversion and propagation (a) Designed on-chip sSPP-TL with mode conversion structure (the underlying shielding metal is not shown), (b) components of the electrical field at four perpendicular planes in (a) at 2 THz, (c) Simulated component at 2 THz evaluated at the xoy-plane 4 Results and discussion 4.1 Comparison with microstrip line and CPW Insertion loss is compared for the microstrip line, CPW and sSPP-TL with different lengths as shown in Fig. 8. Here, the efficient converter is required at both ends of sSPP-TL to reduce the reflection loss while providing a necessary momentum matching at the interface, respectively. The total sSPP-TL length is with two converters included. Obviously, the sSPP-TL has the lowest loss in the broad sub-THz regime, whereas the microstrip line introduces the highest insertion loss. This is because in the sub-THz band, sSPP-TL attenuation can be considered as caused by metal loss only. While the traditional microstrip line suffers the highest radiation loss and CPW is second. Furthermore, with bigger lengths this advantage becomes more vivid. The insertion loss of sSPP-TL stay merely two times to that of its 1 mm long, while the microstrip line suffers more than two times. As can be observed from Fig. 8, for lower frequencies, the insertion loss curves become closer and joint together at lower frequencies. This can also be revealed by dispersion curves, the sSPP-TL works more akin to the microstrip (MS) line in lower frequencies, where . Fig. 8Open in figure viewerPowerPoint Insertion loss comparison for microstrip line, CPW and sSPP-TL with different lengths 4.2 Measurement and results The proposed on-chip sSPP-TL(with pads added) is fabricated in the standard 130 nm BiCMOS technology, which provides four copper thin metals and three alumina thick metals. The length of the whole line (including pads) is , while the sSPP-TL part is long. Fig. 9 shows the fabricated die micrograph of the sSPP-TL, the top metal layer with a thickness of is employed for a periodic groove metal line. The M1 layer is employed as an underlying shielding metal layer. Fig. 9Open in figure viewerPowerPoint Fabricated die micrograph of the proposed sSPP-TL The EM field confinement and efficient mode conversion can be evaluated by measuring the reflection coefficient and the transmission coefficient . The fabricated on-chip SPP-TL structure is measured by using CASCADE Microtech Elite-300 probe station and Keysight PNAX (N5247A) with the Virginia Diodes, Inc. (VDI) extenders providing a signal source from 140–220 and 220–325 GHz. The measurement setup is shown in Fig. 10. The measurement is done in two steps. Firstly, two 140–220 GHz extenders are used together with the vector network analyzers (VNA) calibrated with the line-reflect-reflect-match method to measure the first frequency band. Then, two 220–325 GHz extenders are used to measure the second frequency band with the same calibration method. To get the overall results, these two bands' results are combined together. Fig. 10Open in figure viewerPowerPoint Measurement setup for the sub-THz sSPP-TL The comparison between measured and EM-simulated S-parameters is shown in Fig. 11(different colours are adopted to distinguish two measurement frequency bands). Good agreement between simulation and measurement results is obtained from 140 to 325 GHz. The transmission coefficient presents a low and flat response over the broadband. The measured insertion loss is larger than the simulated one, this may be due to the calibration method and the inaccuracy of the 'cal-kit', especially the probe contact position in the line(thru) standard. Average measured attenuation is 1.07 dB. Therefore, the insertion loss of the sSPP-TL is about 1.54 dB/mm. The reflection coefficient which is lower than −18.5 dB over the all frequency band and presents a good impedance matching characteristic. In the upper measurement, band shows more ripples as compared with the lower measurement band due to a poor calibration. There are many factors that will introduce these ripples, such as long waveguides which introduce lots of insertion loss thus deteriorate the quality of the calibration. As the calibration plane is at the probe-tip plane and may cause a large reflection, which brings ripples on the return loss. Fig. 11Open in figure viewerPowerPoint Comparison of the simulated and measured results 5 Conclusion An on-chip sSPP-TL is investigated in the sub-THz region by using the standard silicon process. The field distribution and dispersion diagram are evaluated by parametric analysis. The proposed on-chip sSPP-TL with a mode conversion structure from GCPW shows a good E-field confinement and transmission efficiency over the broadband operation frequency range. The measured return loss is better than 18.5 dB, and the measured insertion loss is 1.54 dB/mm in average from 140 to 325 GHz. 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