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Universal pilot relaying scheme for series and shunt‐compensated lines

2017; Institution of Engineering and Technology; Volume: 12; Issue: 4 Linguagem: Inglês

10.1049/iet-gtd.2017.0814

1751-8695

Om Hari Gupta, Manoj Tripathy,

Full-Duplex Wireless Communications

IET Generation, Transmission & DistributionVolume 12, Issue 4 p. 799-806 Research ArticleFree Access Universal pilot relaying scheme for series and shunt-compensated lines Om Hari Gupta, Om Hari Gupta orcid.org/0000-0001-6171-809X Department of Electrical Engineering, Dayalbagh Educational Institute, Agra, IndiaSearch for more papers by this authorManoj Tripathy, Corresponding Author Manoj Tripathy manojfee@iitr.ac.in Department of Electrical Engineering, IIT Roorkee, Roorkee, IndiaSearch for more papers by this author Om Hari Gupta, Om Hari Gupta orcid.org/0000-0001-6171-809X Department of Electrical Engineering, Dayalbagh Educational Institute, Agra, IndiaSearch for more papers by this authorManoj Tripathy, Corresponding Author Manoj Tripathy manojfee@iitr.ac.in Department of Electrical Engineering, IIT Roorkee, Roorkee, IndiaSearch for more papers by this author First published: 17 January 2018 https://doi.org/10.1049/iet-gtd.2017.0814Citations: 10AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract The fault component power and energy-based relaying schemes find limitation during the double phase to ground faults due to the effect of mutual coupling. In this study, a pilot relaying scheme for series and shunt-compensated transmission lines is introduced which is based on incremental reactive power coefficients (IRPCs). The IRPC of a phase is defined as the ratio of integrated incremental reactive power (IIRP) to the maximum magnitude of IIRP among all three phases. If IRPC of any phase is found less than −0.5, the internal fault is detected else if none of the phases has IRPC less than −0.5, the fault is an external fault. The algorithm will start only if the incremental differential current of any phase is found >50% of pre-fault differential current. The proposed scheme has various advantages including universal applicability to protect the series and shunt-compensated transmission lines. The offline and real-time simulations are carried out to investigate the performance of the proposed scheme under different operating conditions. The scheme is robust and accurate for all the conditions. Further, the performance of the proposed scheme is superior to the recently proposed schemes. 1 Introduction Flexible AC transmission system (FACTS) device pushes more power through the transmission line (TL). However, it seriously disturbs the TL protection. The thyristor-controlled series capacitor (TCSC) causes several problems such as voltage/current reversals which affect the protection schemes [1, 2]. So the conventional protection techniques may lead to a failure in the presence of TCSC in the TL. Similarly, shunt FACTS devices may also under/over reach and cause the failure of conventional relaying schemes [3, 4]. Therefore, a new universal protection scheme is required which should be immune to the disturbances caused by the series and shunt FACTS devices. The directional relaying scheme can be used for the protection of TLs, if the relays of both the ends communicate to each other in the case of a forward fault. In [5–7], different directional relaying schemes are proposed for the TLs. However, these schemes can only detect the fault and cannot classify the type of fault. In [8], analysis of directional elements is conducted which concludes that the change in source impedance leads to malfunction the directional element. Several fast directional schemes are proposed in [9–13]. However, scheme of [9] uses high sampling rate and requires distinct relays. In [10, 11], the power system is assumed reactive and fault classification problem is not discussed. The scheme of [12] may fail since there will be no traveling wave appearance if a fault befalls at zero inception angle. Similarly, the energy-based scheme [13] cannot be used to classify the fault type since energy depends on fault location, type, and resistance. A fault component integrated power (FCIP)-based pilot relaying scheme is presented in [14] recently. The FCIP is obtained using per-phase calculation basis and the effect of mutual coupling is not considered. It is found that for a line-to-line-to-ground (LL-G) fault, mutual coupling effect is large on the FCIP and the fault is mis-detected as a line-to-ground (L-G) fault. Besides all the limitations mentioned above, the relaying scheme should also be universally applicable irrespective of the load level and compensation type, level, and mode. The universal applicability prevents from the excessive expenditure required to update/replace the relay in the case of any changes/modifications occur in the transmission network. Therefore, this article proposes an incremental reactive power coefficients (IRPCs)-based pilot relaying scheme applicable to both the series and shunt-compensated TL. Since modern digital relays are all equipped with synchronisation facility using global positioning system (GPS) technology and newly built TLs are also equipped with high-speed communication channels [15], the pilot-based relaying scheme can be preferred. Using the incremental (or superimposed) voltage and current phasors, IIRP is first obtained as (1) where m and n denote the relay ends, p denotes the phase (i.e. p = a, b, and c) and , , and are the incremental complex power, voltage, and current, respectively, at end-x (x = m and n) of phase-p. For internal fault, IIRP is negative and for external fault, it is positive. However, its dependency on fault type, location, and resistance makes it difficult to select a fixed threshold for fault-type classification. Therefore, to resolve this problem, IRPCs are introduced. IRPC is given as (2) where ΔQmax = max(ΔQp) for p = a, b, and c. It is clear from (2) that the magnitude of IRPC will always lie between −1 and +1. For an external fault, IRPC should be +1 and for an internal fault, IRPC should be −1. However, considering 50% safety margin, if IRPC of any phase is found less than −0.5, an internal fault is detected else it is an external fault. All the phases with IRPCs less than −0.5 are the faulty phases. If more than one phases are found faulty, a multi-phase fault identified else it is a single-phase fault. To avoid any false detection due to load change or any other disturbance, the proposed algorithm will initiate only if the incremental differential current (ΔIdp) of any phase is more than 0.5Idpre, where Idpre is the pre-fault differential current. The proposed scheme is unaffected by the harmonics due to the presence of TCSC or static VAR compensator (SVC) since it uses the fundamental phasors of the measured voltages and currents using discrete Fourier transform. Additionally, the scheme is stable and accurate for different operating conditions such as load change, power swing, variations in compensation level, type, and mode, and different fault locations, types, and resistances. 2 Integrated incremental active and reactive powers The incremental quantity refers to a quantity which is the difference between pre-fault and fault quantities. Following is the derivation for internal and external fault in series/shunt-compensated TLs. 2.1 Internal fault Consider an internal fault at F1 in series and shunt-compensated lines as shown in Fig. 1. The equivalent incremental single-phase circuit can be represented as depicted in Fig. 2. From figure, it is clear that the incremental voltage at end-m is characterised by m -side network and can be defined as (3) Fig. 1Open in figure viewerPowerPoint Single-line diagrams (a) Series, (b) Shunt-compensated TL Fig. 2Open in figure viewerPowerPoint Incremental diagrams of FACTS-compensated TL (a) Internal fault in series-compensated TL, (b) Internal fault in shunt-compensated TL, (c) External fault in series-compensated TL, (d) External fault in shunt-compensated TL The incremental complex power at end-m can be written as (4) Similarly, the incremental voltage at end-n is characterised by n -side network and therefore, the incremental complex power is given as (5) The integrated incremental complex power is defined as (6) Since , following outcome is expected: (7) (8) It is observed from (7) and (8) that both the integrated incremental active power (IIAP) and IIRP are negative for an internal fault. 2.2 External fault Consider an external fault in both the series and shunt-compensated lines at F2 as shown in Fig. 1. The corresponding incremental single-phase equivalent circuits are illustrated in Fig. 2c and d. It can be observed that the incremental voltage at end-m is characterised by the entire network in front of end-m, i.e. line network including n -side network while the incremental voltage at end-n is characterised by n -side network only. Therefore, the incremental voltages at end-m and end-n can be written as follows: (9) (10) where for series-compensated TL and for shunt-compensated TL. Using (9) and (10), the integrated incremental complex power for both the series and shunt-compensated lines can be written as (11) The IIAP and IIRP of (11) can be written as follows: (12) (13) Since the shunt charging impedance and shunt compensating device impedance are always much higher in magnitude than that of line series impedances. So the following assumptions can be made. and therefore, it can be written as Therefore, both (12) and (13) are positive in the case of an external fault. It is clear that for an internal fault, both the IIAP (i.e. FCIP) and IIRP should be negative while they should be positive for an external fault. However, it is not always true, i.e. FCIP-based scheme finds limitation in the case of an LL-G fault due to the mutual coupling effect. In the case of TL protection, the mutual coupling effect cannot be ignored; therefore, the effect of the mutual coupling is discussed next. 3 Effect of the mutual coupling Consider the positive, negative, and zero sequence networks of a series-compensated line for an internal fault at F1 as depicted in Figs. 3a–c, respectively. Here, only series-compensated line is taken into consideration but the outcome will also be the same for the case of a shunt-compensated line as already proved in Section 2. From Fig. 3, the phase-a incremental voltage at end-m can be obtained as (14) where and . Fig. 3Open in figure viewerPowerPoint Incremental sequence diagram of series-compensated TL for an internal fault (a) Positive sequence, (b) Negative sequence, (c) Zero sequence Similarly, incremental voltages of other two phases at end-m can be obtained. The incremental complex power of phase-a at end-m can be obtained as (15) Similarly, phase-b and phase-c incremental complex powers at end-m can be obtained. 3.1 Single-L-G fault Consider an a–g fault at F1 as shown in Fig. 3. In this case, ΔImb and ΔImc are negligible compared with ΔIma and therefore, incremental complex powers of all three phases will be (16) (17) (18) The positive and zero sequence impedances of the power system are highly inductive in nature. Therefore, it can be assumed that and is a real number. Hence, both real and imaginary parts of (16) are negative. Similar conclusion will be observed at end-n which means that both the IIAP (i.e. FCIP) and IIRP of phase-a are negative. Moreover, the incremental complex powers of phase-b and phase-c are negligible compared to that of phase-a and are close to zero as given in (17) and (18), respectively. Overall, both the FCIP and IIRP successfully detect the L-G fault. 3.2 LL and 3-ph (LLL) faults During LL faults and LLL faults, the zero sequence current does not exist. Therefore, (15) will have only first term. So the incremental complex powers can be written as follows: (19) Now, for an ab fault, ΔIma and ΔImb are very high and ΔImc is nearly zero. Therefore, real and imaginary parts of and are negative while that of are nearly zero. Similar conclusion can be obtained at end-n which means that IIAP and IIRP of phase-a and phase-b are both negative. Therefore, FCIP and IIRP both can detect an LL (multi-phase) fault successfully. Similarly, for a 3-ph fault, ΔIma, ΔImb, and ΔImc are very high. Therefore, FCIPs and IIRPs of all three phases are negative and detecting a 3-ph (multi-phase) fault. 3.3 LL-G fault Now, let us consider an internal ab–g fault at F1 as shown in Fig. 3. In this case, ΔIma and ΔImb are very high and ΔImc is close to zero. Incremental complex power of phase-a at end-m can be rewritten as This equation of incremental complex power of phase-a can further be modified as (20) Similarly, for phase-b, it will be (21) The incremental complex power of phase-c will be negligible and can be written as (22) where , , , and Fig. 4 depicts the plots of incremental active and reactive powers (IAP and IRP), which are obtained using (20) and (21) considering unity magnitudes of , , and . The usual value of km is nearly 2.4 [5] and, θZ is 87°, θI is nearly 150° for ab–g fault. It is clear from Fig. 4a that the IAP of phase-a is negative while that of phase-b is positive even if the value of km varies from 1 to 2.5. On the other hand, in Fig. 4b, the IRP of phase-a and phase-b both are negative for all values of km. The phasor diagram corresponding to (20) and (21) is given in Fig. 4c. Again, it is clear that due to the presence of mutual coupling, the IAP of one phase becomes positive (though it should be negative), whereas the IRPs of both the phases are negative for an ab–g fault. Overall, for an ab–g fault, IIRP of phase-a and phase-b both is negative. On the contrary, IIAP (or FCIP) of one of the phases (phase-b) is positive. Therefore, IIRP detects an ab–g fault successfully while FCIP detects an a–g fault and finds limitation. Fig. 4Open in figure viewerPowerPoint Effect of variations in km and phasor diagram of incremental complex power as per (20) and (21) (a) IAP, (b) IRP, (c) phasor diagram 4 Implementation of the proposed scheme The incremental components during normal operating conditions should remain zero. However, they are not exactly zero due to several factors such as load variations, switching transients, and noise and therefore, (15) may result in some IIRP. Therefore, to avoid this possible false detection, the algorithm will start only if the magnitude of incremental differential current () is >50% of the magnitude of pre-fault differential current (0.5Idpre). This setting for incremental differential current is chosen so that proposed relaying can be started for high-resistance faults up to 500 Ω. Further, incremental differential current is used just as an alert signal and final decision is made by the proposed scheme. Now, the internal fault can be detected when the following conditions are satisfied: (23) However, in (23), since the magnitude of IIRP (ΔQp) depends on the fault type, location, and resistance, it will be difficult to choose a threshold for the identification of faulty phase. To address such challenge, IRPCs are introduced in this work. The IRPCs are obtained for each phase as given in (2). For an external fault, IRPC should be +1 and for an internal fault, it should be −1. However, considering 50% safety margin, if IRPC of any phase is found less than −0.5, the internal fault is detected. Therefore, the modified criterion for internal fault detection is given as follows: (24) The value of Kp can be obtained using (2). If two or more phases are found having IRPCs below −0.5, a multi-phase fault is identified else single-phase fault is spotted. This helps facilitating single-pole tripping in the case of a single-phase fault. 5 Performance investigation of the proposed scheme For the performance investigation of the proposed scheme, the TCSC and SVC-compensated lines are considered. The offline simulation package PSCAD/EMTDC is used for the evaluation and then a real-time digital simulator (RTDS) is used for a real-time validation of the proposed scheme. The performance of the scheme has been investigated for many situations such as variations in the fault location, fault resistance, compensation level, load level, and source impedance. The scheme is also found stable and unaffected by the power swing and CT, CVT, and sample synchronisation errors. However, due to space limitation, this section reports results of a few cases only. 5.1 Offline evaluation using PSCAD/EMTDC A two-terminal TCSC and SVC-compensated TLs are used for the evaluation as shown in Fig. 1. An additional line (i.e. line A) is added to the left of TCSC of Fig. 1a and protected line, i.e. line B (between ends m and n) is 30% TCSC compensated. The parameters of the transmission system are taken from [5]. Other details are given as follows: line voltage: 400 kV, line A: 50 km, line B: 250 km, frequency: 50 Hz, CT ratio: 1500 A/1 A, CVT ratio: 231 kV/100 V. Similarly, a 300 km, 50 Hz, and 400 kV SVC-compensated two-terminal TL [15] is illustrated in Fig. 1b, which is also considered for the evaluation of the proposed scheme. In all the tables containing IRPCs, if the magnitude of incremental differential current (ΔIda) is found less than the corresponding threshold (0.5Idpre), IRPCs are not calculated; instead, '#' is kept in the tables. 5.1.1 Effect of fault location, compensation level, and load level For two TCSC compensation levels, Table 1 contains the IRPCs obtained for different fault locations. The location of the fault is the distance of fault from end-m. The negative distances represent the external faults at F2 side. It can be observed from Table 1 that during all the internal faults, IRPCs of faulty phases are less than −0.5 while the IRPCs of healthy phases are greater than −0.5. For 30% compensation, an ab–g fault is created at 150 km and the incremental differential current (ΔIdp) of phase-a is shown in Fig. 5a. The IRPCs are calculated only when ΔIda exceeds 0.5Idpre. As per Fig. 5b, Ka, Kb, and Kc are −0.91, −1.00, and −0.01, respectively. The faulty phases are clearly distinguished and therefore, proposed relaying clearly identifies the internal fault and classifies the fault type. All the results presented in next sections are recorded with TCSC compensation level of 30%. Fig. 5Open in figure viewerPowerPoint ab–g fault at 150 km with 30% compensation level (a) Incremental differential current, (b) IRPCs Table 1. IRPCs for different fault locations and TCSC compensation levels Fault location, km Fault type 30% compensation 70% compensation Ka Kb Kc Ka Kb Kc 0 a–g −1.00 −0.01 −0.01 −1.00 −0.01 −0.01 ab –g −0.73 −1.00 −0.01 −0.81 −1.00 −0.01 50 3-ph −0.87 −1.00 −0.68 −0.91 −1.00 −0.89 ab −0.97 −1.00 −0.01 −0.98 −1.00 −0.01 100 ab −0.97 −1.00 −0.01 −0.99 −1.00 −0.01 3-ph −0.94 −1.00 −0.72 −0.84 −1.00 −0.96 150 a–g −1.00 −0.01 −0.01 −1.00 −0.01 −0.01 ab–g −0.91 −1.00 0.01 −0.96 −1.00 0.01 250 3-ph −1.00 −0.95 −0.83 −1.00 −0.98 −0.91 ab −0.99 −1.00 −0.01 −0.99 −1.00 −0.01 −0 3-ph 0.94 1.00 0.90 0.92 1.00 0.89 ab–g 0.74 1.00 −0.14 1.00 0.86 −0.08 −25 ab 0.99 1.00 −0.01 0.99 1.00 −0.01 a–g # # # # # # The SVC varies the injected reactive power as per the variations in the SVC tap voltage. Therefore, instead of varying SVC compensation level, Table 2 comprises the IRPCs obtained for different types of solid faults at different locations in SVC-compensated TL with the line load angles (δ) of 30° and 45°. As can be seen in Table 2, during all the internal faults, IRPCs of faulty phases are less than −0.5 while the IRPCs of healthy phases are greater than −0.5. Therefore, proposed relaying scheme successfully detects the internal faults and classifies the type of faults in the case of shunt-compensated TL also. Table 2. IRPCs for different fault locations and load levels in SVC-compensated TL Fault location, km Fault type δ = 30° δ = 45° Ka Kb Kc Ka Kb Kc 0 a–g −1.00 −0.01 −0.01 −1.00 −0.01 −0.01 ab–g −1.00 −0.94 −0.01 −0.98 −1.00 −0.01 50 3-ph −1.00 −0.88 −0.89 −0.98 −1.00 −0.88 ab −0.99 −1.00 −0.01 −1.00 −0.97 −0.01 100 ab −0.99 −1.00 −0.01 −1.00 −0.92 −0.01 3-ph −1.00 −0.98 −0.91 −1.00 −0.84 −0.86 150 a–g −1.00 −0.13 −0.11 −1.00 −0.10 −0.14 ab-g −1.00 −0.89 −0.14 −1.00 −0.95 −0.12 250 3-ph −1.00 −0.92 −0.86 −0.90 −1.00 −0.88 ab −0.99 −1.00 −0.01 −1.00 −0.95 −0.01 300 ab −0.99 −1.00 −0.01 −1.00 −0.98 −0.01 3-ph −1.00 −0.96 −0.86 −0.94 −1.00 −0.88 −0 a–g 1.00 0.01 −0.04 1.00 −0.01 −0.01 Ab 1.00 0.99 −0.01 0.94 1.00 −0.01 3-ph 1.00 0.90 0.94 0.91 1.00 0.96 5.1.2 Effect of current/voltage reversal The current and voltage reversal problems are present in the case of series compensation. These cause nuisance to the TL relaying schemes. In the test system (with 70% series compensation) used in this study, the current reversal is present in all the internal faults occur at a distance of 0–81 km from end-m and the voltage reversal is present from 82 to 175 km. The results are already taken at the fault locations lie within these two ranges and are included in Table 1, which clearly show the successful detection of internal fault. Therefore, proposed scheme is unaffected by the current/voltage reversals. 5.1.3 Effect of metal oxide varistor (MOV) conduction MOV protected series compensating device can be approximated by a variable capacitor in series with a variable resistor [16]. Therefore, during the conduction of MOV, a high value of resistance is included in the series of compensating device. During an internal fault, the establishment of proposed scheme depends on the source side parameters, and not on the internal line parameters. Therefore, MOV conduction will have no impact during internal faults. In the case of external faults, MOV conduction will affect the real component of (15) (i.e. FCIP), not the imaginary component (15) (i.e. IIRP). Therefore, MOV conduction will not disturb the operation of the proposed scheme. 5.1.4 Effect of different fault resistance Firstly, the proposed pilot relaying has been verified for a–g faults with different fault resistances (Rf) in TCSC-compensated TL. The obtained IRPCs are presented in Table 3. From the table, it is observed that the internal faults are spotted as well as the fault type is also identified. Table 3. IRPCs for different fault resistances in TCSC-compensated TL Fault location, km Rf, Ω Ka Kb Kc 0 100 −1.000 0.001 0.001 300 −1.000 0.001 0.001 500 −1.000 −0.002 −0.002 50 100 −1.000 0.002 0.002 300 −1.000 0.001 0.001 500 −1.000 −0.001 −0.001 150 100 −1.000 0.001 0.001 300 −1.000 0.001 0.001 500 −1.000 −0.001 −0.001 250 100 −1.000 −0.005 −0.004 300 −1.000 −0.004 −0.004 500 −1.000 −0.004 −0.004 −25 100 # # # 300 # # # 500 # # # Similarly, the proposed scheme has been tested for a–g faults with different fault resistances in SVC-compensated TL. Table 4 includes the IRPCs and indicates that the internal faults have been detected and type of fault is classified successfully. Further, to compare the performance of proposed scheme with the differential current scheme, differential currents are also obtained and included in Table 4. The differential current setting is selected above two times the pre-fault differential current [17]. The pre-fault differential current is 544.47 A and therefore, the differential current setting should be above 1.1 kA. It is observed from Table 4 that differential current has the limitation of detecting high resistance faults. Faults with resistances of 300 Ω and above are not detected by the conventional differential current scheme. However, the proposed scheme successfully detects the high resistance faults. Table 4. IRPCs for different fault resistances in SVC-compensated TL Fault location, km Rf, Ω Ka Kb Kc Ida, kA 0 100 −1.000 −0.001 −0.001 2.39 300 −1.000 −0.001 −0.001 1.06 500 −1.000 −0.002 −0.001 0.81 100 100 −1.000 −0.022 −0.029 1.76 300 −1.000 −0.018 −0.033 0.87 500 −1.000 −0.019 −0.033 0.70 200 100 −1.000 −0.021 −0.029 1.70 300 −1.000 −0.018 −0.032 0.84 500 −1.000 −0.017 −0.033 0.67 300 100 −1.000 −0.002 −0.001 2.21 300 −1.000 −0.002 −0.001 0.93 500 −1.000 −0.002 −0.001 0.70 −0 100 # # # 0.44 300 # # # 0.47 500 # # # 0.48 5.1.5 Effect of high source impedance The equivalent source impedance in a real power system is not always constant and varies continuously. Therefore, in order to observe the impact of variation in the source impedance, the positive and zero sequence impedances of the source at end-m side in TCSC-compensated line are increased by four times to their previous values. The obtained results are included in Table 5 which indicates that the proposed scheme is unaffected since internal fault is detected and type of the fault is classified successfully. Similar outcome has been observed in the case of an SVC-compensated TL shown in Fig. 1b. Table 5. IRPCs for faults with high source impedance in a TCSC-compensated TL Fault location, km Fault type Ka Kb Kc 0 a–g −1.000 −0.007 −0.005 ab–g −1.000 −0.954 −0.005 50 ab–g −1.000 −0.865 −0.003 a–g −1.000 −0.003 −0.004 100 3-ph −1.000 −0.925 −0.875 ab −1.000 −0.987 −0.001 150 a–g −1.000 −0.133 −0.130 ab–g −1.000 −0.932 −0.179 200 3-ph −0.978 −1.000 −0.903 ab −1.000 −0.994 −0.001 250 a–g −1.000 −0.003 −0.006 ab −1.000 −0.995 −0.001 300 3-ph −1.000 −0.966 −0.863 ab −1.000 −0.999 −0.001 −0 a–g 1.000 −0.017 −0.013 ab 0.978 1.000 −0.001 3-ph 1.000 0.897 0.904 5.1.6 Effect of evolving fault Evolving fault is a single-phase fault (primary fault) converting to multi-phase fault (secondary fault). The performance of the proposed scheme is evaluated for evolving fault in a TCSC-compensated TL. First, an a–g fault is created at time 0.6 s and then converted to an ab–g fault after 25 ms [18]. The obtained IRPCs are depicted in Fig. 6. It can be seen that initially, phase-a is detected as faulty phase since Ka is less than −0.5 but after the occurrence of secondary fault, phase-b is also detected as faulty phase because Kb also falls below −0.5. Fig. 6Open in figure viewerPowerPoint IRPCs for evolving fault at 100 km from end-m 5.1.7 Comparison with recent FCIP-based scheme Recently, a relaying scheme based on fault-FCIP [14] is proposed for TL. The term FCIP is nothing but the IIAP in this study. Figs. 7a and b present the IIAP (ΔP) and IIRP (ΔQ), respectively, for an ab–g fault at 50 km (at F1) in an SVC-compensated line [15]. It can be seen that IIAP classifies this fault as an a–g fault since only ΔPa is negative while IIRP identifies it as an ab–g fault since both ΔQa and ΔQb are negative. Therefore, FCIP [14] and energy-based schemes may fail to classify the type of fault accurately. This study has presented a rigorous investigation about the reason of this failure in Section 3.3. Similar observation can also be made for TCSC-compensated TL. Fig. 7Open in figure viewerPowerPoint IIAP and IIRP for an internal fault at F1 in SVC-compensated TL (a) IIAP or FCIP, (b) IIRP 5.1.8 Speed of the relaying It has been observed from the results that the relay detects the fault in <20 ms. Now, if the communication delay due to the carrier is also included, the scheme will still be capable to detect an internal fault within the specified time [19]. In case of communication channel failure, adaptive distance relays and/or overcurrent relays are generally provided as backup protection [15]. 5.2 Real-time validation of proposed scheme using RTDS The proposed pilot relaying scheme is successfully validated in a real-time environment using RTDS for various system conditions of TCSC and SVC-compensated TLs mentioned earlier. However, results of some representative cases have been reported here. The RTDS test results are obtained for the validation of the proposed IRPC-based scheme. The TCSC-compensated TL with 30% TCSC compensation is used for validation. The layout of laboratory arrangement is illustrated in Fig. 8. With the help of RSCAD software, the power system model and proposed relaying scheme are emulated in the RTDS processors. RSCAD is a user-friendly software which provides the working environment for a real-time simulation using RTDS [20]. The relay output and incremental differential currents are obtained at the terminals of giga-transceiver analogue output card of RTDS. These outputs are within the range of ±10 V. Similarly, the GTAI card can be used to give any input to the RTDS within the range of ±10 V. The digital storage oscilloscope is used to capture the outputs obtained from RTDS. Fig. 8Open in figure viewerPowerPoint Laboratory arrangement of real-time simulation using RTDS Fig. 9 shows the RTDS results obtained for internal and external faults, respectively. An ab–g internal fault is created at 125 km from end-m and a 3-ph external fault is created 50 km behind end-m in a TCSC-compensated TL. It is observed from Fig. 9a that for internal ab–g fault, IRPCs of phase-a and phase-b are negative and less than −0.5 while that of phase-c is nearly zero. Therefore, scheme detects a multi-phase internal fault. On the contrary, IRPCs of all three phases are positive and are nearly +1 in Fig. 9b indicating an external fault. Similarly, an ab–g fault is created in an uncompensated TL with the same model but without TCSC. When an internal ab–g fault is created at 125 km from end-m, the incremental differential current, Ka, Kb, and Kc are depicted in Fig. 9c. While for an external ab–g fault at 50 km behind end-m, Fig. 9d shows the incremental differential current and relay outputs (i.e. Ka, Kb, and Kc). From Fig. 9c, it is clear that internal fault is detected as a multi-phase fault since Ka and Kb are negative and less than −0.5. In the case of an external fault, IRPCs are positive which is clear from Fig. 9d. Fig. 9Open in figure viewerPowerPoint Relay output for different scenarios (a) ab –g internal fault in a TCSC-compensated TL, (b) 3-ph external fault in a TCSC-compensated TL, (c) ab –g internal fault in an uncompensated TL, (d) 3-ph external fault in an uncompensated TL 5.3 Advantages of the proposed scheme The proposed pilot relaying scheme has several advantages over the existing relaying schemes which are given as No need to change/update/replace the relay (and relay setting) in the case of any change in the line configuration since the same relay threshold (−0.5) can be used in all the cases. The pre-fault differential current is used to activate the proposed algorithm and in the case of any change in the type of compensation and its level, the pre-fault differential current will change. However, since this pre-fault differential current is readily available from the CT measurements situated at both relay ends (i.e. end-m and end-n), proposed scheme is completely unaffected by any modifications in the transmission network. Therefore, proposed scheme prevents from the excessive expenditure required to update/replace the existing relays in the case of any possible modification and can be used for both the series and shunt-compensated TL. Therefore, the proposed relaying scheme can be called a universal relaying scheme. The proposed scheme is also unaffected by the measurement and sample synchronisation errors. Also, the scheme is stable in the case of power swing. 6 Conclusion Existing protection schemes are first reviewed and then a universal pilot relaying scheme for series and shunt-compensated TL has been introduced which is unaffected by the mutual coupling effect during asymmetrical fault. This scheme uses the incremental reactive power for the criterion establishment. Different offline and real-time simulations using series and shunt-compensated TLs have been carried out for performance evaluation and validation. The scheme is found stable, secure, selective, and accurate for the variations in the fault location, fault resistance, compensation level, load level, and source impedance. The scheme performs better while compared with recently proposed FCIP-based scheme. Additionally, the proposed scheme is applicable to both the series and shunt-compensated TLs with identical relay threshold. Since the modern relays are equipped with the facility to synchronise the data using GPS facility and the newly built TLs are also equipped with the high-speed communication channel, the proposed pilot relaying scheme can attract the protection engineers. 7 References 1Biswal, M., Pati, B.B., Pradhan, A.K.: 'Adaptive distance relay setting for series compensated line', Int. J. Electr. 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