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A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2

2017; Institute of Electrical and Electronics Engineers; Volume: 63; Issue: 3 Linguagem: Inglês

10.1109/tce.2017.014908

1558-4127

Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong Kim, Han-Young Hong, Young‐Chan Jang,

Analog and Mixed-Signal Circuit Design

A 2.5-Gbps/lane receiver bridge chip, which fully supports the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) camera serial interface (CSI)-2, is proposed for a field-programmable gate array (FPGA)-based frame grabber. The proposed receiver bridge chip converts four-lane high-speed data of scalable low-voltage signaling (SLVS) of the MIPI CSI-2 into 32 low-speed data of low-voltage CMOS (LVCMOS) signaling for a parallel interface with a FPGA chip. In order to achieve this, each data lane of the proposed receiver bridge chip has a 1-to-8 deserializer including a byte synchronizer. Furthermore, an asynchronous delay line per lane compensates the time skew among the five lanes, including a clock lane. A common-gate level shifter (CGLS) with a continuous-time linear equalizer (CTLE) is proposed to improve the voltage gain and bandwidth of the high-speed receiver. The proposed receiver bridge chip is implemented using a 0.11-μm CMOS process with a 1.2 V supply. The area and power consumption of the proposed receiver bridge chip are 5.29 mm2 and 7.2 mW/Gbps/lane, respectively. The proposed CTLE of the high-speed receiver achieves the improved peak-to-peak time jitter of 0.311I at a data rate of 3.0 Gbps/lane. The FPGA-based frame grabber processes the image or video data supplied by a camera sensor with the MIPI CSI-2 by using the proposed receiver bridge chip.