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nMOS Transistor Location Adjustment for N-Hit Single-Event Transient Mitigation in 65-nm CMOS Bulk Technology

2017; Institute of Electrical and Electronics Engineers; Volume: 65; Issue: 1 Linguagem: Inglês

10.1109/tns.2017.2783935

1558-1578

Zhenyu Wu, Shuming Chen,

VLSI and Analog Circuit Testing

Heavy-ion experiments demonstrated that reducing the distance between nMOS transistor and n-well can reduce N-hit (i.e., hit nMOS transistor) single-event transient (SET) pulsewidth. This principle can be applied for radiation-harden-by-design standard cell design without any area overhead. TCAD simulations indicated that the guard drain effect of the n-well and the enhanced restore current of pMOS transistor are responsible for the N-hit SET pulsewidth reduction.