Produção Nacional
Revisado por pares
Comparative analysis of network‐on‐chip simulation tools
2017; Institution of Engineering and Technology; Volume: 12; Issue: 1 Linguagem: Inglês
10.1049/iet-cdt.2017.0068
ISSN1751-861X
AutoresSarzamin Khan, Sheraz Anjum, Usman Ali Gulzari, Frank Sill Torres,
Tópico(s)Advanced Memory and Neural Computing
ResumoIET Computers & Digital TechniquesVolume 12, Issue 1 p. 30-38 Research ArticleFree Access Comparative analysis of network-on-chip simulation tools Sarzamin Khan, Corresponding Author Sarzamin Khan khan.szamin@yahoo.com Department of Electrical Engineering, COMSATS Institute of Information Technology, Wah Cantt, PakistanSearch for more papers by this authorSheraz Anjum, Sheraz Anjum Department of Computer Science, COMSATS Institute of Information Technology, Wah Cantt, PakistanSearch for more papers by this authorUsman Ali Gulzari, Usman Ali Gulzari Department of Electrical Engineering, COMSATS Institute of Information Technology, Islamabad, PakistanSearch for more papers by this authorFrank Sill Torres, Frank Sill Torres Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, BrazilSearch for more papers by this author Sarzamin Khan, Corresponding Author Sarzamin Khan khan.szamin@yahoo.com Department of Electrical Engineering, COMSATS Institute of Information Technology, Wah Cantt, PakistanSearch for more papers by this authorSheraz Anjum, Sheraz Anjum Department of Computer Science, COMSATS Institute of Information Technology, Wah Cantt, PakistanSearch for more papers by this authorUsman Ali Gulzari, Usman Ali Gulzari Department of Electrical Engineering, COMSATS Institute of Information Technology, Islamabad, PakistanSearch for more papers by this authorFrank Sill Torres, Frank Sill Torres Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, BrazilSearch for more papers by this author First published: 05 December 2017 https://doi.org/10.1049/iet-cdt.2017.0068Citations: 16AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract Network-on-chip (NoC) is a reliable and scalable communication paradigm deemed as an alternative to classic bus systems in modern systems-on-chip designs. Consequently, one can observe extensive multidimensional research related to the design and implementation of NoC-based systems. A basic requirement for most of these activities is the availability of NoC simulators that enable the study and comparison of different technologies. This study targets the analysis of different NoC simulators and highlights its contributions towards NoC research. Various NoC tools such as NoCTweak, Noxim, Nirgam, Nostrum, BookSim, WormSim, NOCMAP and ORION are evaluated and their strengths and weaknesses are highlighted. The comparative analysis includes methods for estimation of latency, throughput and energy consumption. Further, the exemplary real world application, video object plane decoder is mapped on a 2D mesh NoC using different mapping algorithms under NOCMAP and NoCTweak simulators for comparative analysis of the NoC simulators and their embedded mapping algorithms. 1 Introduction Modern integrated system designs incorporate the system-on-chip (SoC) technology in order toimprove performance, costs and energy consumption. Embedded SoC systems arecomprised of intellectual property (IP) cores, memory units, processors etc. [[1]]. In the state-of-the-art SoC designs, theseblocks are connected by traditional busses to communicate and exchange data witheach other. However, beyond a certain number of elements, bus-based systemsencounter their communication limitations due to high power consumption, highbandwidth requirements and high latency [[2]].Hence, the network-on-chip (NoC) paradigm has been proposed as an alternativesolution to these communication bottlenecks. Bus-based systems enable communicationamong the resources via custom busses, shared busses, hierarchical busses or busmatrix as shown in Fig. 1. Fig. 1Open in figure viewer Embedded system categories In contrast, NoC-based systems include 2D, 3D mesh, Tree and Torus NoC designs. Alsohybrid design of these architectures may be adopted [[3], [4]]. NoCs apply packet based switching for on chip communication. The packets enable the exchange ofdata among processing elements (PEs), using resource network interfaces (RNI),routers and interconnecting links as shown in Fig. 2. Routers forward packets across the network and may consist of input/outputbuffers, routing logic, allocators and crossbars [[5]]. Links/Channels enable the interconnection of the routers for datatransmission. They are usually bidirectional and multi-layered. RNI is theinterfacing unit between the PEs and the router. RNI and router collectively work asresource network router. Its function is to packetise and de-packetise the messagesfor processing and routing across the network. PE is the functional block thatprocesses the data and may be an IP core, a memory element, a Processor etc. Fig. 2Open in figure viewer Elements of a common NoC The NoC architecture is specified by its topology, routing algorithm and flow control. Here, topology means the physical ordering and arrangement of the links connecting the network nodes. Exemplary topologies are Mesh, Torus, Folded Torus and Tree [[6], [7]]. The routing algorithm defines how messages between PEs traverse the network. Routing may be deterministic or adaptive. A good routing algorithm will balance the traffic load across the network and should avoid deadlock and live-lock. Flow control is the allocation of communication resources for guaranteed and reliable transmission of packets between the PEs. In other words, flow control allocates the resources like buffers and link bandwidth to the messages as they traverse through the network [[8]-[10]]. NoCs are generally evaluated with respect to their performance parameters, such as energy consumption, area, communication bandwidth, throughput and latency [[11]]. Several simulators have been designed in order to evaluate these parameters and predict the system's performance prior to the design implementation [[12]-[26]]. Some simulators like ORION [[12], [13]] only focus on the performance of individual components, e.g. router power and area, while others such as Noxim, Nirgam and NoCTweak [[14]-[17]], are designed for measurement of the entire network performance. ORION simulator is used as a standard model for the estimation of energy of a router and link of the network. It is usually embedded in other network simulators (e.g. Noxim, Nirgam) to calculate the energy of the entire network. There are other energy models like CMOS standard library model [[17]] and Bit energy model [[27]] which are also used for estimation of the network energy consumption. As NoC inherits many features from general computer networks, so these network simulators can also be used for NoC system simulations [[28]-[32]]. Having in mind the rising amount of different simulators, this work is an attempt to provide a road-map that facilitates the selection of appropriate tools. This paper is organised as follows: Section 2 presents related work on NoC simulators. Section 3 describes briefly the representation of NoC applications and Section 4 relates to the comparative analysis of NoC simulators. Simulation results are evaluated in Section 5 and concluding remarks are presented in Section 6. 2 Related work Current research is mostly involved in topology design, router design, routing protocols, mapping and scheduling techniques [[33]]. Only limited study is available about NoC tools comparisons and surveys [[34]-[42]]. The work presented in [[37]] discusses some NoC proposals and contributions regarding their attainable capabilities. The author has collected a few NoC tools from the literature and presented a short description of the characteristics of the simulators. A comprehensive study is carried out about NoC concepts, but the survey lacks the comparative analysis of the NoC performance measurements. In the research work of Neuenhahn [[38]], static and dynamic performance analysis of NoC is performed and evaluated at different abstraction levels. The static performance analysis has included timing models, while dynamic performance models are composed of FPGA, VHDL, Colored Petri Nets and SystemC-based simulations. Comparative analysis of different modelling techniques showed significant deviations in term of performance parameters of the simulators. The author has presented a quantitative analysis of the tools regarding their structure, but focused only on general aspects of the NoC tools. The study in [[39]] presented an overview of the NoC concepts and simulation tools. Furthermore, the recent contributions on simulation tools are highlighted. The survey presented in [[40]] reviewed different approaches for NoC traffic models and performance evaluation. In this work, the evaluation-based analytical models and the design challenges of the NoC simulators are discussed, but only a descriptive study is presented about the NoC tools. The author of research work in [[41]] presented a short comparison of the HNOCS simulator with a few NoC simulators and highlighted the contribution of HNOC to the NoC research. The work presented in [[42]] collected numerous programming models and proposal for MPSoC but did not discuss dedicated NoC simulators. Availability of 3D, optical and wireless NoC simulators are also limited, because it is a new research area for the research community. It is an open problem for future NoC research to design specific simulators for NoC designs. 3 Representation of NoC applications NoC systems are generally represented by characterisation graphs. Different simulators extract data from these graphs for performance simulations. An application can be represented by network task graph (NTG), which is subsequently scheduled on the available IPs through network core graph (NCG). NCG is then transformed and mapped on NoC packet switched network architecture through NoC architecture graph (NAG). In this work, these characterisation graphs are used to input data to the NoC simulators for comparative analysis and are briefly discussed in the following sections. 3.1 Network task graph An NTG is a directed acyclic graph, Gr = Gr(T, C) in whichvertex of the graph characterises a task, (ti ЄT, i = 1, 2, 3,…) for the computationalresource of the application and represents information, such as execution time,energy consumption, task deadlines as shown in Fig. 3a. The directed arc (ci,j Є C, i = 1, 2,3,…, j = 1, 2, 3,…) represents either data or dependentinformation between processing tasks (ti andtj). The arc(ci,j) is associated with a value (v(ci, j)), whichcharacterises the communicating data that are exchanged between the processingtasks. A real application is usually represented by NTG, which providesnecessary information about the application for processing and simulations asshown in Fig. 3b. Fig. 3Open in figure viewer Representation of embedded applications(a) NTG,(b) VOPD application,(c) NCG,(d) NAG 3.2 Network core graph An NCG, Gr′ = Gr′(P, A), is a directed graph in which vertex of the graph (pi Є P) represent the PE, while the directed arc (ai, j Є A) shows characteristic parameters between the PEs (pi to pj) as shown in Fig. 3c. An arc (ai, j) is associated with communication information, e.g. rate and volume, of communicating data and may have system design constraints, e.g. required latency and data bandwidth. NCG intrinsically represents the scheduling of the tasks (T) on the available PEs (P) for processing. When P = T, or P > T then a single task can be scheduled on an individual PE, but when P < T, then two or more tasks should be scheduled on a single PE. For this purpose, a scheduler is required before performance simulations. 3.3 NoC architecture graph NAG, A = A(R, H), is an architecture graph, in which each vertex (ri Є R) means a router (node) in the graph, while a directed arc (hi, j Є H) indicates the bidirectional routing channel between the routers (ri) and (rj) as shown in Fig. 3d. Arc (hi, j) is associated with Mi, j (set of minimum paths from ti to tj) and L(mi, j) that represents the set of all links associated with mi,j. The cost of the arc is represented by e(hi, j) which shows the average consumption of energy (joule) of sending data between network tiles (ti and tj), e.g. Ei, j (bit). NAG represents the mapped applications on NoC tiles, which is then simulated on a specific tool for performance measurements. To evaluate the potential of NoC simulators for mapping real application on NAG, video object plane decoder (VOPD) application is considered in this research work. The NTG of VOPD consists of 16 distinct tasks as shown in Fig. 3b. In this case, we assume that the tasks are equal to the available processors, therefore scheduling is not required. The NTG and NCG have one to one mapping, so we directly input the NTG to NoCTweak and NoCMAP for simulation as discussed in Section 5.2. 4 NoC simulators A common challenge of selecting the right NoC simulator is that available tools usually are strong in certain measurements and having deficits in others. NoC simulator can be divided into two broad categories: (1) General network simulators that can be used for NoC simulations (e.g. NS2, NS3, Omnet++, Wattch, Hotspot, Netsim, Gem5, Graphite, Hornet, Opnet, Fusionsim, Esece) [[28]-[32]]. (2) Specific NoC simulators, which are explicitly designed for NoC simulation (e.g. BookSim, HNOCS, WormSim, Ocsim, Vnoc, Matrics, SICOSY, Tpzsimul, Garnet, SUNMAP, Ocintsim, Noxim, Nostrum, Nirgam, Occn, Nocsim, NoCTweak, Atlas, Gpnocsim, Xmulator, NONMAP, ReliableNoC, MapoNoC, Phoenixsim, Access Noxim and ORION) [[12]-[26], [43]-[48]] (Table 1). In this section, we describe some important simulators for NoC-based designs. Fig. 4 depicts the block diagram of ageneric NoC simulator with its characteristic parameters. The NoC simulator may havethe following input parameters: (1) Configuration options: Configuration options definethe type of application traffic simulated on the NoC tool. It may besynthetic traffic patterns or embedded application traces. It may alsohave a seed value selection for the simulation, log file for simulationoutputs, warm-up time for the network to become stable and simulationrun time selection. Fig. 4Open in figure viewer Generic NoC simulator (2) Synthetic options: Synthetic options define the sizeand type of topology for the traffic like 2D mesh and the type ofsynthetic traffic pattern such as random, transpose, bit-complement,bit-reverse, bit-shuffle, bit-rotate and hotspot routers selection. Thehotspots are routers in the network that receive packetised data at ahigher rate that they can handle. This phenomenon reduces systemperformance and can lead to deadlocks. An intelligent routing algorithmcan prevent the formation of hotspots. (3) Embedded application traces: Embedded applicationsare real application task graphs used in the simulation such as a VOPD,multimedia system, multi window display, MPEG4 decoder and E3Sbenchmarks. (4) Mapping option: Mapping option such as near-optimalmapping (NMAP), simulating annealing (SA), branch and bound (BB) shouldalso be included for obtaining optimised latency, throughput and energyconsumption. (5) Traffic options: Traffic options include the numberof flits injected by each core per cycle (flit injection rate), theprobability distribution of the period between two injected packets,packet length and flits per packet selection. (6) Router settings: Router settings provide the type ofrouter such as wormhole router, virtual channel router, shared queuesrouter, bufferless router and circuit-switched router. It also definespipeline type, the number of pipeline stages and buffer depth etc. (7) Routing options: Routing options define routingalgorithm like XY dimension-ordered routing, west-first, north-last andodd-even (OE) minimal adaptive routing. It may also have an output portselection such as the X dimension first, the dimension nearest to thedestination first, the dimension farthest to the destination first,round-robin among output ports, the output port with highest creditfirst, switching arbitration policy and inter router link length. (8) Technology settings: It includes CMOS technologyprocess (e.g. 90, 65, 45, 32, 22 nm), clock frequency and supply voltageselection. (9) Measurement options: The output measurementsparameters include throughput, power, latency and energy consumption.The results of the output performance parameters predict the behaviourof the NoC multicore system before physical implementation. Table 1. Comparison of NoC simulators Simulator NoCTweak [[17]] Noxim [[15], [16]] Nirgam [[14]] Nostrum [[19]] BookSim [[18]] WormSim [[49]] NOCMAP [[27], [50]] ORION [[12], [13]] language system C system C system C system C C++ C++ C++ C++ topology 2D mesh 2D mesh 2D mesh, torus 2D mesh, torus wide range 2D mesh, torus 2D mesh no traffic pattern synthetic, embedded synthetic synthetic, embedded synthetic synthetic synthetic, embedded synthetic, embedded no switching mechanism wormhole virtual channel, Roshaq,bufferless, circuits switched wormhole with virtual channel wormhole with virtual channel, wormhole with virtual channel wormhole with virtual channel wormhole with virtual channel wormhole with virtual channel user design buffer depth option yes yes yes yes yes yes yes yes routing algorithm XY, negative first, west first, northlast, OE, lookup table XY, negative first, west first, northlast, OE, dyad, fully adaptive, lookup table source routing, XY, OE XY, deflection routing all XY, OE, dyad XY, OE, west first, dyad no performance parameters power/energy consumption, throughput,latency energy, throughput, communicationdelay power, latency, throughput latency, throughput, linkutilisation latency, throughput energy energy, reliability router power, link power, routerarea energy model CMOS standard cell library model ORION model ORION model no no ORION/bit energy model bit energy model ORION model input parameters interface command line command line log file command line log file command line command line command line hotspot option yes yes no no no yes no no mapping NMAP, random no manual manual no no BB, SA no 4.1 NoCTweak NoCTweak is a SystemC-based simulator developed by Tran and Baas [[17]] for NoC. It is designed for early exploration of performance, e.g. throughput, latency and energy estimation of NoC designs. NoCTweak uses standard CMOS library cell data for post layout timing and power estimation. The simulator has a command line interface for changing input simulation parameters. The current version of the simulator is designed only for 2D mesh topology, but has the option of synthetic and embedded traffic pattern. The hotspot and mapping options, i.e. random and NMAP algorithm for mapping the IPs are included. The router design selection, switching strategies, CMOS technology process selection, frequency and voltage selection are also included in this simulator. 4.2 Noxim Noxim is developed by Maurizio Palesi, Davide Patti and Fabrizio Fazzino at the University of Catania [[15], [16]]. It is a SystemC-based simulator having a command line interface for changing input parameters. The simulator is based on ORION power model and currently designed for 2D mesh topology with only synthetic traffic pattern and wormhole router design. Energy, throughput and communication delay are its output statistic parameters. The input parameters include network size, packet size, packet injection rate, buffer depth, routing strategies and traffic distribution. The routing algorithms include XY, negative-first, west-first, north-last, OE, dyad, fully adaptive and lookup table based. 4.3 Nirgam Nirgam is developed by Lavina Jain as a joint collaboration between the University of Southampton, UK and Malaviya National Institute of Technology, India [[14]]. It is an open source discrete event, cycle accurate simulator for NoC. The current version of the simulator is designed for 2D mesh and torus topologies. The wormhole switching mechanism is adopted in which packet consists of head, body and tail flits. Number of virtual channels, buffer size and clock frequency can also be changed for simulation. The simulator support source, XY and OE routing mechanism. Traffic option includes source/sink and synthetic generator which may be constant bit rate, bursty or input traced based. Performance parameters include average latency per packet (in clock cycles), average latency per flit (in clock cycles) and average throughput (in Gbps) for each channel. 4.4 Nostrum Nostrum is a cycle accurate, layered NoC simulator written in SystemC and python by the Nostrum Team at Royal Institute of Technology (KTH), Stockholm [[19]]. It supports 2D mesh and torus topology with wormhole store and forward switching mechanism. The routing algorithms are XY and deflection order routing. It has the ability of mapping an application to the nodes of the network. The user can also change the arbitration policy and buffering options. It can be configured for both best effort and guaranteed communications. Best effort communication provides average performance, but better utilisation of network resources. Guaranteed communication is based on time division multiplexing with virtual circuits to insure guaranteed latency and throughput. 4.5 BookSim BookSim is an interconnected network simulator written in C++ [[18]]. This simulator can simulate a wide range of topologies, e.g. 2D mesh, torus, concentrated mesh, fat tree, butterfly, flattened butterfly, quad tree and user specific any net etc. The simulator support input queued router and event-driven router micro-architecture with virtual channel support. The performance parameters are either latency or throughput versus offered load. The simulators also support changing buffer size, routing mechanism and arbitration policy. Currently, it only supports synthetic traffic patterns. 4.6 NOCMAP/reliableNoC NOCMAP is an open source mapping simulator of NoC written in C++ by Hu et al. [[27], [50]]. Two mapping algorithms such as BB and SA are implemented in this tool. It uses the bit energy model to calculate the minimum total communication energy of the NoC. BB mapping algorithm is used for topological placement of IPs onto NoC platform to minimise total communication energy consumption. The link bandwidth is considered as constraint parameter. For comparison, ad-hoc SA method is also implemented, which indicates that BB is faster than SA technique with comparable results. Based on the bit energy model EPAM (XY, OE and WF), which is energy and performance aware mapping with different routing algorithm (XY, OE and west-first), an efficient BB algorithm is implemented in this simulator. For comparison, SA algorithm is also implemented which shows that the proposed algorithms are more efficient than SA regarding result optimality and simulation speed. Moreover, it is observed that EPAM-OE gives more accurate results when applied to real and complex applications with large system size. ReliableNoC is an extended version of NOCMAP simulator which has the addition of reliability parameter in NOCMAP simulator. 4.7 ORION Architectural power estimation is an important factor in designing NoC-based systems. ORION is a fast and accurate architectural power model for router power and area simulation of NoC [[12]]. ORION 3.0 [[13]] is its latest release after ORION 1.0 and ORION 2.0. ORION 2.0 and ORION 3.0 have some additional functionality as well as closest performance parameters to the actual NoC designs. The comparison between ORION 2.0 simulations and Intel 80-core actual power consumption of Link, FIFO, Clock, Arbiter and Crossbar closely verify the simulation results of ORION 2.0 simulator. 4.8 Component-based interconnection network simulator (CINSim) CINSim is a general purpose simulator for communication networks developed by a research group at Technische University Berlin (Real-Time Systems and Robotics) [[28], [29]]. The core of the simulator is written in C++ and has a command line interface. The editor of the simulator is written in JAVA and is platform independent. The graphical user interface (CINSim GUI) of the simulator is through an XML file of XML. The simulator has the capability of simulating both regular and irregular communication networks. The performance parameters are throughput, delay and latency. The network components are source buffers, non-shared buffers, routers, target buffers, routing and switching techniques and scheduling algorithms. Like NS-2 it can also be used for NoC simulations. 5 Comparative simulations To carry out comparative analysis of NoC tools, a generic configuration setup is described inorder to evaluate each simulator on the basis of its metrics of performance. Theavailable simulators do not have a common approach for input/output parameterselection and also have different simulation models, so it is difficult to preciselyscrutinise each simulator. Therefore a common configuration setup is selected insuch a way that it has same input parameters for comparison. Parameters inTable 2 are used for analysis of thetools. Table 2. Platform description Platform Description Remarks topology 2D mesh most widely used network size 5 × 5 (25 nodes) selected for simulation workload/benchmark synthetic most simulators support fixed packet length 10 flits nominal size flit injection rate 0.1–0.7 flits/cycle/node range 0–1 traffic type uniform predictable results router type wormhole most common routing algorithm XY commonly supported buffer size 8 flits selected for simulation input voltage 1 V selected for simulation operating clock frequency 1000 MHz selected for simulation warm-up time 20,000 cycles for accuracy Most of the available simulators support 2D mesh, synthetic traffic pattern,wormhole switching mechanism, buffer depth availability and XY routing algorithm.Throughput, latency and power are the output characteristics parameters of thesesimulators. In this research work, the results of different simulators are compared on the basis of a unified configuration setup for a 5 × 5, 2D mesh. The input parameters and the design structure of most of the simulators are different, so it is difficult to precisely compare all the simulators on a unified configuration setup. It is tried to compare some of these simulators on the basis of a best uniform approach. 2D mesh of size 5 × 5 is selected, because most of the simulator support 2D mesh topology and size 5 × 5 is chosen to minimise simulation time. 5.1 Synthetic benchmark For comparison of NoC simulators, synthetic benchmark is selected because some simulator such as Noxim and CinSim support only synthetic traffic pattern. Injected traffic is also limited to 0.7 flits/cycle/node, in order to avoid network traffic congestion. In latency analysis, it is observed that Noxim and Nirgam have almost the same latency trend with injected traffic (flit injection rate) as shown in Fig. 5a. NoCTweak and CinSim have a non-linear response at low traffic, but when flit injection rate exceeds 0.5 flits/cycle/node; their response is comparable with Noxim and Nirgam. It may be due to the fact that NoCTweak and CinSim requires some extra parameters for analysis, which are limited in Noxim and Nirgam. Variations in the results are also due to the unavailability of an exact and uniform embedded platform in these simulators. The design structure of these simulators is also different from each other. Fig. 5Open in figure viewer Performance parameters of NoC simulators(a) Network latency of NoCTweak, Noxim, Nirgam and CINSim, (b) Network throughput of NoCTweak, Noxim and CinSim, (c) Average energy of NoCTwek and Noxim, (d) Network power of NoCTweak and Nirgam Fig. 5 (continued)Open in figure viewer Performance parameters of NoC simulators(a) Network latency of NoCTweak, Noxim, Nirgam and CINSim, (b) Network throughput of NoCTweak, Noxim and CinSim, (c) Average energy of NoCTwek and Noxim, (d) Network power of NoCTweak and Nirgam In throughput calculations (Fig. 5b), variation in results of NoCTweak is observed at the start, but the response is closely matched to that of Noxim and CinSim at a slightly high injection rate. Similarly, in Network energy analysis, NoCTweak and Noxim have a minor difference in results with the same injected traffic as shown in Fig. 5c. It is due to the fact that Noxim uses ORION energy model [[13], [14]] while NoCTweak utilises CMOS standard cell library model [[17]]. In network power calculations (Fig. 5d), again the results of NoCTweak and Nirgam are comparable and almost have the same trend at a high injection rate. 5.2 Real application benchmark NoCTweak and NOCMAP have the ability to map a real application on NoC tiles for energyoptimisation. A VOPD (Fig. 3b) is simulated on these simulators for energycomparison. VOPD has 16 tasks and therefore requires 4 × 4, 2D mesh forimplementation. NoCTweak has built in random and NMAP mapping algorithms, whileNOCMAP utilises BB and SA algorithms. In NoCTweak, the mapping through NMAPalgorithm has 23.52% improvement in energy when compared with random algorithmsas shown in Table 3. Table 3. VOPD application energy and simulation time comparison NoCTweak randommapping NoCTweak NMAPmapping NOCMAP BBmapping NOCMAP SAmapping energy consumption, pJ/flit 34.56 26.43 29.90 30.01 simula
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