Constrained Level Validation of Serial Peripheral Interface Protocol
2017; Springer Nature; Linguagem: Inglês
10.1007/978-981-10-5544-7_73
ISSN2190-3026
AutoresAvinash Yadlapati, Kakarla Hari Kishore,
Tópico(s)Embedded Systems Design Techniques
ResumoThe motivation behind this paper is to give a full portrayal of a state-of-the-art SPI master/slave usage. Every single related issue, beginning from the elaboration of introductory details, till the last framework confirmation, is thoroughly examined and justified. In similarity with outline reuse approach, the concerned paper imparts high-grade intellectual properties i.e., IP's that concerns in gathering all essential components that help in achieving presently required and modern ASIC or SoC applications using this SPI master and slave protocol. SPI is a standout among the most usually utilized serial interface protocols.
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