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High throughput hardware architecture for accurate semi-global matching

2017; Elsevier BV; Volume: 65; Linguagem: Inglês

10.1016/j.vlsi.2017.12.007

1872-7522

Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, Song Chen,

Image Enhancement Techniques

As the most important step of a stereo vision system, stereo matching, which finds the correspondences in stereo image pairs, requires high-quality real-time depth computation. In this paper, a high throughput and high accuracy full-pipeline hardware architecture with disparity and row parallelism is proposed. In the semi-global aggregation stage, to improve the accuracy in discontinuous regions, adaptive weighted path costs are adopted, and, five aggregation paths are used without consuming external memory resources. Finally, L-R check, spike removal and disparity confidence check handle the outlier regions to enhance the disparity map. Disparity map quality evaluations on Middlebury benchmark and real-world outdoor scenery show that the proposed implementation is able to generate high quality disparity maps. The proposed hardware architecture is implemented on a Stratix V FPGA, which results in a throughput of 1280 × 960/197 fps with 64 disparity levels at 156 MHz. Compared with the latest work, we can get 1.48 times speedup and use 19% more memory with much less computation resources (34.5% less ALUTs and 46.1% less Regis-ters).