Impedance matching theory to design an all‐optical AND gate
2018; Institution of Engineering and Technology; Volume: 12; Issue: 5 Linguagem: Inglês
10.1049/iet-opt.2018.0020
ISSN1751-8776
AutoresHaraprasad Mondal, Mrinal Sen, Chandra Prakash, Kamanashis Goswami, Champak Kumar Sarma,
Tópico(s)Plasmonic and Surface Plasmon Research
ResumoIET OptoelectronicsVolume 12, Issue 5 p. 244-248 Research ArticleFree Access Impedance matching theory to design an all-optical AND gate Haraprasad Mondal, Corresponding Author Haraprasad Mondal mandal.haraprasad@gmail.com Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorMrinal Sen, Mrinal Sen Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorChandra Prakash, Chandra Prakash Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorKamanashis Goswami, Kamanashis Goswami Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorChampak Kumar Sarma, Champak Kumar Sarma Electronics and Communication Engineering Department, Dibrugarh University, Dibrugarh, Assam, 786004 IndiaSearch for more papers by this author Haraprasad Mondal, Corresponding Author Haraprasad Mondal mandal.haraprasad@gmail.com Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorMrinal Sen, Mrinal Sen Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorChandra Prakash, Chandra Prakash Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorKamanashis Goswami, Kamanashis Goswami Electronics Engineering Department, Indian Institute of Technology (I.S.M.), Dhanbad, Jharkhand, 826004 IndiaSearch for more papers by this authorChampak Kumar Sarma, Champak Kumar Sarma Electronics and Communication Engineering Department, Dibrugarh University, Dibrugarh, Assam, 786004 IndiaSearch for more papers by this author First published: 01 October 2018 https://doi.org/10.1049/iet-opt.2018.0020Citations: 7AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract An impedance matching theory-based methodology is presented in this study for designing/optimising photonic crystal-based all-optical AND gate. A basic architecture for the AND gate is projected first, and thereafter the same is optimised utilising the proposed methodology. Performance of the AND gate is evaluated based on several metrics that are calculated using a finite-difference-time-domain simulation. The optimised AND gate has exhibited a high extinction ratio in the order of 6.9 dB, within a very small footprint of . It also supports propagation of a high bit rate (≈1 Tb/S) and has a wide operational bandwidth (≈4 THz), which make the device suitable for different photonic integrated circuit applications. 1 Introduction Density of integration and speed of operation of electronic devices are rapidly driving to their saturation, as the miniaturisation of electronics is approaching to the atomic level of silicon [1]. In this context, 'photonics' is one of such technologies which promise to remove these limitations. A long and sustained research in this area has well nourished this technology to make it capable of delivering potential components for photonic integrated circuits (PICs) [2] such as amplifier [3], multiplexer and demultiplexer [4, 5], decoder [6], logic gates [7], polariser [8]. However, it is quite challenging as well as crucial to mould the flow of light in photonics, and majority cluster of researchers depends on photonic crystal (PhC) [2, 9–11] structures for the same. This is because, the geometric arrangement of the lattice of a PhC, which offers a photonic band gap (PBG) for guiding the wave, can easily be modulated to control the optical propagation of a desirable band of frequencies. Thus, recently a number of researchers have reported PhC-based photonic switches and logic components [12–14] for the future generation PICs. Among these, the Boolean logic component AND gate is inevitable for many applications and, hence, different structures have been proposed towards its design. For example, Andalib and Granpayeh [13] have proposed an all-optical AND gate based on Kerr non-linear PhC ring resonators, which supports a data rate of ≈120 Gbps. Similarly, Pashamehr et al. have also reported [15] an all-optical AND/OR/NOT gate based on PhC ring resonators utilising the Kerr non-linearity. However, due to non-linearity, these devices require considerable amount of powers for its logic inputs to maintain a sustained extinction ratio (ER), as well as their operations. On the other hand, linear photonics do not demand a minimum threshold of input powers, but designing logic devices in linear optical regime is quite challenging. In this regard, Younis et al. have shown [16] operations of all-optical OR and AND gates in linear optical regime using a combination of ring cavity and Y-shape line defect coupler. Fasihi [17] has proposed a simple design of square-lattice dielectric-rod PhC structure, where a dielectric rod has been placed in the junction of the two input-waveguides to implement an all-optical AND gate that has an ER of 6 dB. However, the device cannot perform well in the long chain of similar circuitries as the maximum output power, at a logic '11' input, is merely 50% of its input power. Similarly, Rani et al. [18] have designed an AND gate using a 2D air-hole triangular lattice PhC with a point defect in the junction. However, the ER of the gate is 1 Tb/s . Fig. 8Open in figure viewerPowerPoint Time-evolving graph for the output power 3.6 3D FDTD simulation on the final 2D-slab structure In order to evaluate performance of the device in practical regime, the optimised model has been redesigned in a 2D-slab structure as shown in Fig. 9 a. The structure is considered to be built on a silica slab, where silica rods are considered to be extended for 2 μm over the silica slab. The 5 μm long silicon rod structures are considered to be built above these silica rods, over which 2 μm long silica rods are again considered to be formed to maintain symmetry in the vertical direction of the structure. Rest of the design parameters are kept constant as previous. Now, this structure has been simulated using a 3D FDTD method under the excitation of input logic levels '01', '10' and '11'. The corresponding electric field distributions through the structure are shown in Figs. 9 a –d, respectively. It is evident from these figures that the design and corresponding operations are persistent even in a finite 3D slab structure. Fig. 9Open in figure viewerPowerPoint The 3D view of PhC-Slab and it's corresponding electric field profile at various input conditions (a) The 3D representation of AND gate, (b) Electric field profile at logic '01' inputs, (c) Electric field profile at logic '10' inputs, (d) Electric field profile at logic '11' inputs 3.7 Comparative study with other optical AND gates A comparative study on the performances of similar type of AND gates has been presented in Table 2. The following paragraph details the study as shown in the table. Andalib et al. [13] and Pashamehr et al. [15] have reported optical AND gates based on non-linear ring resonators. However, requirement of threshold input power, large footprint, low data-rate, and small output power at logic '1' make these devices less-attractive members within their family. Ring resonators and Y-shaped junctions have been used in [16, 26] to realise optical AND gates, in linear optical regime, having an ER of ≈6 dB. However, their footprint sizes are considerably large and the data-rates are moderate, which limit them to be chosen for a PIC application. Also, the self-collimation property of 2D PhC has been used in [27] to design an optical AND gate, but the ER and output power at logic '1' is comparatively small. On the other hand, Fasihi [17] has proposed an AND logic gate in a 2D square-lattice PhC using the properties of linear optics. Although the gate shows a good contrast ratio and its footprint is moderately small, the output power at logic '1' is substantially low. The work also sites applicability of cavity mode theory in its design but no explicit consideration of design methodology based on this theory has been mentioned. Similar strategies have been adopted by Rani et al. [18, 28]; however, they have considered a Y-shaped junction in different configurations of PhC to design their AND gate. Nevertheless, in contrast to the present work, none of the above reports adopts a specific methodology for designing/optimising their work. Thus, the application of impedance matching theory-based design and optimisation procedure has led us to achieve an AND gate that offers a high contrast ratio as 6.9 dB, a considerably high output power at logic '1', and a moderately high bit-rate in a considerably small footprint size. Table 2. Comparative study of different optical AND gates Reference Type of crystala Output power as logic-1b Output power as logic-0b Contrast ratio (dB) Data rate, Tbps Footprint size (μm2) [13] RiA 0.656 I/P 0.13 I/P 6.93 0.12 253 [15] RiA — — — — 396 [16] RiA — — 6 0.208 572 [26] RiA 1.0 I/P 0.25 I/P 6 0.83 863 [27] RiA 0.75 I/P 0.25 I/P 4.9 — 100 [17] RiA 0.5 I/P 0.125 I/P 6 — 296 [18] HiS 1.58 I/P 0.395 I/P 6.02 0.83 — [28] HiS 1.63 I/P 0.414 I/P 5.95 3.33 64 this work RiA 1.26 I/P 0.26 I/P 6.9 1 110 a RiA, rods in air; HiS, holes in slab. b I/P is the maximum of the input powers. 4 Conclusion A basic design of a PhC-based all-optical AND gate is proposed in this work. An impedance matching theory is devised and adopted to optimise the basic design of the AND gate. For the same, the design is divided into two parts, and impedances of both the parts are calculated. The radius of a rod in the Y-junction is varied and the corresponding variations in impedance are recorded for different types of input excitations (those represent different logic combinations). Finally, match/mismatch of impedances of the left section with that of the right one is enhanced at the desired/undesired logic combinations by optimising the radius. Thereafter different performance metrics such as power transfer, propagation profile, ER, TR and response time are evaluated for the optimised AND gate. Power transfer and TR of the device for different logic combinations ensure its logical operation as of the desired gate for a wideband (≈30 nm) of wavelengths. The high TR at the logic '1'output also confirms the repeatability of the device in a long chain of circuit. The high ER (≈6.9 dB) offered by the device makes it convenient for maintaining large noise margin and low BER. Also, the fast response time (≈0.25 ps) confirms the allowable bit rate in the range of 1 Tb/s. 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