Family of zero voltage transition interleaved converters with low voltage and current stress
2018; Institution of Engineering and Technology; Volume: 11; Issue: 12 Linguagem: Inglês
10.1049/iet-pel.2017.0656
ISSN1755-4543
AutoresBaharak Akhlaghi, Morteza Esteki, Hosein Farzanehfard,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoIET Power ElectronicsVolume 11, Issue 12 p. 1886-1893 Research ArticleFree Access Family of zero voltage transition interleaved converters with low voltage and current stress Baharak Akhlaghi, Baharak Akhlaghi orcid.org/0000-0001-5365-4057 Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111 IranSearch for more papers by this authorMorteza Esteki, Morteza Esteki Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111 IranSearch for more papers by this authorHosein Farzanehfard, Corresponding Author Hosein Farzanehfard hosein@cc.iut.ac.ir Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111 IranSearch for more papers by this author Baharak Akhlaghi, Baharak Akhlaghi orcid.org/0000-0001-5365-4057 Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111 IranSearch for more papers by this authorMorteza Esteki, Morteza Esteki Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111 IranSearch for more papers by this authorHosein Farzanehfard, Corresponding Author Hosein Farzanehfard hosein@cc.iut.ac.ir Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111 IranSearch for more papers by this author First published: 19 September 2018 https://doi.org/10.1049/iet-pel.2017.0656Citations: 6AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract This study presents a family of zero voltage transition (ZVT) interleaved converters which utilises a simple auxiliary cell. The ZVT cell has only a single auxiliary switch for multi-phase interleaved converters. In the proposed converters, all semiconductor devices operate under fully soft switching condition. The main switches turn on and turn off under zero voltage switching (ZVS) condition while the auxiliary switch turns on and turns off under zero current switching (ZCS) condition. Besides, all the converter main and auxiliary diodes turn off under ZCS condition which alleviates the diodes reverse recovery problem. The ZVT cell imposes no extra current and voltage stresses on the semiconductor devices. The effectiveness of the proposed method is evaluated by a 100 kHz, 200 W two-phase interleaved boost converter and the theoretical analysis and design procedure are discussed in detail. Furthermore, the results of an implemented laboratory prototype are provided which are consistent with the theoretical analysis. Nomenclature Ceq equivalent capacitance of the snubber capacitor CS in series with the resonant capacitor Ca (F) D main switches duty cycle fsw switching frequency of the main switches S1, S2 (Hz) fswa switching frequency of the auxiliary switch Sa (Hz) IS1, IS2 source current of S1, S2 (A) ID1, ID2 current of the main diodes D1, D2 (A) ISa source current of Sa (A) IDa1, IDa2 current of the auxiliary diodes Da1, Da2, (A) IDa3, IDa4 current of the auxiliary diodes Da3, Da4, (A) Iin average input current (A) IL boost inductor current (A) ILa1, ILa2 current of the auxiliary inductors La1, La2 (A) ΔI current ripple of L1 and L2 (A) Po output power (W) Vin DC input voltage (V) Vo DC output voltage (V) VGS1, VGS2 gate to source voltage of S1, S2 (V) VDS1, VDS2 drain to source voltage of S1, S2 (V) VGSa gate to source voltage of Sa (V) VDSa drain to source voltage of Sa (V) VCa voltage across capacitor Ca (V) ω1, ω3 angular resonant frequency of La1 and Ca (rad/s) ω2 angular resonant frequency of La1 and Ceq (rad/s) ω4 angular resonant frequency of La2 and Ca (rad/s) 1 Introduction Interleaving technique normally parallels n converters of a kind. In this technique, the converters have the same switching frequency with 180/n phase shift. As a result, the converter input/output current ripple and semiconductor devices current stress are reduced. Besides, by interleaving n phases, the effective switching frequency is increased n times. As a result, the transient response is improved and the passive components size and weight are reduced [1, 2]. Therefore, interleaved topologies are very attractive in high power applications like power factor correctors (PFCs), voltage regulators, and renewable energy systems [3-7]. By increasing the switching frequency of interleaved converters, size and transient response of the converter can be further reduced. Nevertheless, high-frequency hard-switched interleaved converters suffer from high switching dissipation and electromagnetic interference (EMI) problem [8, 9]. In order to overcome these problems, soft switching techniques such as zero voltage transition (ZVT) and zero current transition (ZCT) can be used [10-12]. ZVT techniques are preferred since they can eliminate the switch capacitive turn-on losses [13]. In recent years, many ZVT interleaved boost [14-23], buck [11, 12], and buck–boost [24] topologies are introduced in literatures. In all the ZVT interleaved boost converters proposed in [14-18], the main and auxiliary semiconductor devices operate under soft switching condition. The major drawback of these structures is that they need two auxiliary switches to provide soft switching condition for a two-phase interleaved structure which complicates the circuit and increases the converter cost and size. To overcome this drawback, the authors in [19-23] propose two-phase ZVT interleaved boost converters which utilise only one auxiliary switch. However, in structures of [19-21], the auxiliary switch and diode operate under hard switching condition. In this way, excess switching loss and EMI are produced in the converter which can invalidate utilising the ZVT cell. ZVT interleaved boost converter introduced in [22] has the advantage of having no extra current and voltage stresses on the main switches. However, the auxiliary switch current stress is high. A fully soft-switched interleaved boost PFC converter is presented in [23] which uses a single auxiliary switch. Nevertheless, the ZVT cell which employs a transformer is voluminous. Besides, the auxiliary transformer delivers its energy to the load during the whole time which the auxiliary switch is activated. This leads to higher conduction dissipation. A ZVT interleaved buck converter is proposed in [11] which utilises an auxiliary circuit with only one active switch. In this converter all the semiconductor devices operate under soft switching condition. However, the voltage and current stresses of the auxiliary switch are high. An interleaved twin-buck converter with low number of auxiliary elements is presented in [12], however, the converter is frequency controlled and thus, the filter is not optimum. A ZVT interleaved buck–boost converter is presented in [24] with identical soft switching method of the converter introduced in [12] and thus, has the same disadvantages. This paper presents an effective ZVT soft switching technique which utilises an auxiliary circuit with a single auxiliary switch for multi-phase interleaved buck, boost, and buck–boost topologies. The main switches turn on and off under zero voltage switching (ZVS) and the auxiliary switch turns on and off under zero current switching (ZCS) conditions. Furthermore, the converter diodes turn off under ZCS condition and thus their reverse recovery problem is alleviated. Unlike some of the already existing ZVT interleaved converters such as the one introduced in [15], the proposed converters have also proper soft switching performance for duty cycle values less than 0.5. In order to validate the proposed technique, the ZVT cell is applied to an interleaved boost converter. The theoretical analysis, design considerations, and the experimental results of a laboratory prototype interleaved boost converter operating at 200 W and 100 kHz are presented. The ZVT cell is then modified so that it can be applied to a common input–output ground interleaved buck converter. Although the basic ZVT cell was previously introduced in [25] and applied to a single phase boost converter, its applicability on other types of converters and multi-phase interleaved topologies has not been investigated so far. In the present work, the ZVT cell is also modified so that the size of the auxiliary circuit is reduced. 2 Operational analysis 2.1 ZVT interleaved boost converter description Fig. 1 shows the proposed ZVT interleaved boost converter in which L1 and L2 are the boost filter inductors, Co is the output capacitor, S1 and S2 are the main switches, CS1 and CS2 are respectively S1 and S2 snubber capacitors, D1 and D2 are the output diodes, Vin is the input voltage source, Vo is the output voltage, and Ro is the load. The auxiliary circuit, shown in the dashed block, consists of resonant inductors, La1 and La2, resonant capacitor, Ca, auxiliary diodes, Da1, Da2, Da3, and Da4, and auxiliary switch, Sa. Fig. 1Open in figure viewerPowerPoint Proposed ZVT interleaved boost converter 2.2 Steady-state operational analysis It is assumed that the proposed interleaved boost converter operates in continuous conduction mode (CCM) and the duty cycles of two phases are equal. Fig. 2 shows the related key waveforms and Figs. 3–5 show the equivalent circuits of the operational modes for D > 0.5. Eighteen predominant operating modes take place in each switching cycle. Due to the symmetric form of the interleaved structure, only nine of these modes related to one phase are analysed here. Fig. 2Open in figure viewerPowerPoint Key waveforms of the proposed ZVT interleaved boost converter Fig. 3Open in figure viewerPowerPoint Equivalent circuits of operating modes 1–3 of the proposed ZVT interleaved boost (a) Mode 1 [t0-t1], (b) Mode 2 [t1-t2], (c) Mode 3 [t2-t3] Fig. 4Open in figure viewerPowerPoint Equivalent circuits of operating modes 4–6 of the proposed ZVT interleaved boost (a) Mode 4 [t3-t4], (b) Mode 5 [t4-t5], (c) Mode 6 [t5-t6] Fig. 5Open in figure viewerPowerPoint Equivalent circuits of operating modes 7–9 of the proposed ZVT interleaved boost (a) Mode 7 [t6-t7], (b) Mode 8 [t7-t8], (c) Mode 9 [t8-t9] Mode 1 [t0-t1] (Fig. 3a): Prior to t0, S1 and S2 are ON, and other semiconductor devices are OFF. L1 and L2 are being linearly charged by Vin and Co is supplying the load. At t0, S1 is turned off and L1 current, IL1 linearly charges CS1. At t1, CS1 voltage, VCs1 reaches VCs1(t1), and Da1 and Da4 turn on. Important equations of this mode are (1) (2)where VCa(t0) is Ca initial voltage at the beginning of this mode. Mode 2 [t1-t2] (Fig. 3b): During this mode, both CS1 and Ca are being charged linearly by IL1. Therefore, S1 turns off at ZVS. At t2, VCa reaches zero, and simultaneously VCs1 ramps up to Vo and this mode finishes. The governing equations are as follows: (3) (4)The time required for charging CS1 and providing ZVS condition at turn off for the main switch, namely tt1 equals to summation of modes 1 and 2 durations and can be obtained from (1)–(4). Mode 3 [t2-t3] (Fig. 3c): At t2, D1 turns on and transfers L1 energy to the output and L2 continues to be charged by Vin through S2. Other converter semiconductor devices are in OFF state. In this mode, the converter operation is like any regular pulse-width modulation (PWM) interleaved boost converter. Mode 4 [t3-t4] (Fig. 4a): In order to discharge CS1 and turn on S1 at ZVS, Sa is turned on at t3. Due to the presence of La1, the turn ON of Sa and Da1 are at ZCS. A resonance occurs between Ca and La1 through the path of Da1-Ca-La1-Sa. Thus, ILa1 and VCa increase and conversely ID1 decreases in the course of this resonance, and D1 turns off under ZCS at t4. Corresponding equations of this duration are as follows: (5) (6)where (7) (8)As La2 is much larger than La1, the role of La2 in the resonances in modes 4 to 7 can be ignored. Mode 5 [t4-t5] (Fig. 4b): At the beginning of this mode, D1 turns off and a new resonance begins between CS1, Ca, and La1. Through this resonance, CS1 is discharged. At t5, VCs1 reaches zero, and S1 and S2 anti-parallel diodes turn on. The defining equations of this resonance are as follows: (9) (10) (11)where (12) (13) (14) (15) (16)VCa(t4) is Ca voltage at the beginning of this mode. The minimum time required for the main switch to turn on at ZVS, namely tt2 is summation of the durations of mode 4 (t34) and mode 5 (t45) and can be obtained from (5)–(16). In other words, tt2 is the minimum required advanced time before applying the main switch gate signal. Mode 6 [t5-t6] (Fig. 4c): At t5, S1 and S2 anti-parallel diodes turn on and a new resonance begins between Ca and La1. At t6, S1 and S2 anti-parallel diodes turn off at ZCS, and this mode ends. During this mode, S1 can be turned on at ZVS. The defining equations of this mode are as follows: (17) (18)where (19) (20) (21)ILa1(t5) and VCa(t5) are, respectively, La1 current and Ca voltage at the beginning of this mode. Mode 7 [t6-t7] (Fig. 5a): The resonance in the previous mode continues in this mode. At t7, ILa1 decreases to zero and then Sa can be turned off at ZCS. The minimum time taken to reduce ISa from its maximum value (ISa(max) = ILa1(t5)) to zero can be obtained from (17)–(21). The total time that the auxiliary switch must be kept ON to provide ZVS condition at turn on for the main switch and then turns off at ZCS condition, tSa is the summation of tt2 and durations of modes 6 and 7. Mode 8 [t7-t8] (Fig. 5b): At the beginning of this mode, a new resonance occurs between Ca and La2 and the energy stored in Ca transfers to La2. At t8, after half a resonant period, La2 current, ILa2 becomes zero and Da3 turns off at ZCS and the resonance is stopped. L1 and L2 are being charged linearly by the input voltage through S1 and S2, respectively. The important equations are as follows: (22) (23)where (24) (25)and VCa(t7) is Ca initial voltage at the beginning of this mode. The duration of mode 8, namely t78 can be obtained from (22)–(25). The resonance process in mode 8 is finished before turning off the other phase main switch. Mode 9 [t8-t9] (Fig. 5c): During this interval, the converter operates as a regular interleaved boost converter and this mode is identical to DT time of the PWM boost converter. This mode continues until S2 turns off and the next half of switching period starts. 3 Design guideline and example Due to the symmetrical structure of interleaved converters, it is assumed that: L1 = L2, CS1 = CS2, and D1 and D2 and also S1 and S2 are similar. The main switches duty cycles are identical and >0.5. The design guideline for the proposed converter is first explained and then the converter parameters are calculated through an example of a two-phase ZVT interleaved boost converter with the input voltage Vin = 100 V, the output voltage Vo = 400 V, the full load output power Pout = 200 W, and the switching frequency fsw = 100 kHz. 3.1 Converter switches and diodes selection The converter switches and diodes are selected based on the following considerations. The voltage and current stresses of the converter main switches and diodes are as follows: (26) (27)where ΔIL/2 is less than the minimum value of the input current or practically about 10% of the nominal input current. The voltage stresses of the converter auxiliary switch and diodes are as follows: (28) (29)The current stresses of the converter auxiliary switch and the auxiliary diodes Da1 and Da2 can be calculated from (9) (30)The current stress of Da3 is calculated from (22) (31)Also, the current stress of Da4 is equal to that of D1 and D2 (32)From (26), (28), and (29), the voltage stress of the converter semiconductor devices except Da3 is 400 V and the voltage stress of Da3 is 150 V. From (27) and (32), current stress of the main switches, main diodes, and Da4 is 1.1 A. From (30), the current stress of auxiliary switch, and auxiliary diodes Da1 and Da2 is about 5.7 A. Finally, from (31) the current stress of auxiliary diode Da3 is 3.3 A. 3.2 Converter filter inductor and capacitor selection The converter boost inductors, L1 and L2 and the output capacitor, Co are designed like those of a regular boost converter [26, 27]. A 100 μF capacitor is selected for Co and the inductance of L1 and L2 is 500 µH. 3.3 Auxiliary circuit elements selection The snubber capacitors, CS1 and CS2 are designed like regular snubber capacitors and are selected in such a way that can appropriately control dv/dt of main switches voltages at turn off transition at the worst case [28] (33)where IS1 is S1 current before removing S1 gate signal, and tf is S1 current fall time. Two 1 nF capacitors are selected as snubber capacitors. The value of Ca must be selected larger than the value of CS1 and CS2, so that VCs1 changes more quickly than VCa in mode 5. Thus, (12) and (13) can be, respectively, rewritten as (34) (35)The resonance period in mode 5 (T2) must be chosen much smaller than the switching period (36)From (35) and (36) (37)Besides, the peak current value of the resonance in mode 4, established by (5), must be greater than ID1, so that CS1 can be discharged in mode 5 (38)By substituting for Z1 from (8) (39)The proper values for La1 and Ca which satisfy both (37) and (39) inequalities would be 5 µH and 12 nF, respectively. By selecting these values, tt1 = 1.4 µs, tt2 = 0.13 µs, and tSa = 0.4 µs. The resonance between Ca and La2 in mode 8 is finished before removing the main switch gate signal. Therefore, this resonance period, T4 must meet the following condition: (40)From (24) and (40) (41)The maximum value of La2 can be calculated from (41). However, it is important to note that if a smaller value is selected for La2, the peak value of the resonant current in (22) would be higher and this increases the conduction loss. Besides, La2 value must be selected greater than La1, so that VCa polarity remains positive in modes 6 and 7. In this way, ILa1 can become zero and Sa can achieve ZCS at turn off. Considering this point and (41), a proper value for La2 would be 20 µH, and t78 would be about 1.5 µs. Therefore, summation of transient intervals, tt1 + tt2 + t78 is equal to about 3 µs which is 30% of the switching period. The values of converter elements are listed in Table 1. Table 1. Proposed converter parameters Parameter Symbol Specification main switches switching frequency fsw 100 kHz auxiliary switch switching frequency fswa 200 kHz output capacitor Co 100 µF snubber capacitors CS1, CS2 1 nF resonant capacitor Ca 12 nF boost inductors L1, L2 500 µH resonant inductor La1 5 µH resonant inductor La2 20 µH main and auxiliary switches S1, S2, Sa IRFP460 main and auxiliary diodes D1, D2, Da1-Da4 MUR460 4 Experimental results and comparison A laboratory prototype of the proposed converter with parameters specified in Table 1 is implemented and tested to validate the theoretical analysis. The prototype operates under CCM condition. Fig. 6 shows the experimental waveforms of the main switch S1, voltages and currents at nominal load, half load, and at 20% of nominal load conditions. This figure clearly illustrates how the main switch turns on and off under ZVS condition even at light loads. Besides, as can be observed from this figure, the voltage and current stresses of the main switch at full load is about 400 V and less than 1.8 A, respectively, which are like the ones in conventional interleaved boost converter and hence, no extra voltage and current stresses are imposed on the main switch. Fig. 7a shows the voltage and current waveforms of the auxiliary switch, Sa at nominal load. From this figure, ZCS turn on and turn off of Sa can be seen, which is in contrast to the converter introduced in [19] in which its auxiliary switch turns off at hard switching condition. Fig. 7a also shows that the auxiliary switch current stress is about 2.5 times the main switch current stress which is smaller than 3.3 for the converter introduced in [23]. Besides, from Fig. 7a, the voltage stress of the proposed converter auxiliary switch is equal to the output voltage, while in [23] this value is 25% more than its output voltage. Fig. 7b shows the voltage and current waveforms of the output diode D1 at nominal load. As this figure shows, D1 achieves ZCS at turn off and therefore its reverse recovery problem is alleviated. Fig. 7c shows the resonant elements Ca and La2 voltage and current waveforms. Fig. 6Open in figure viewerPowerPoint Experimental voltage and current waveforms of main switch S1 (a) At full load, (b) At half load, (c) At 20% load Fig. 7Open in figure viewerPowerPoint Experimental voltage and current waveforms of auxiliary switch Sa, output diode D1, and resonant capacitor Ca and resonant inductor La2 at full load (a) Sa, (b) D1, (c) Ca voltage and La2 current A loss breakdown for the proposed and conventional hard switching converters is provided in Table 2. As can be observed, the total loss associated with semiconductor elements in the proposed topology is reduced from 16.9 W to 10.3 W as compared to the hard switching counterpart. The efficiency curves of the proposed ZVT interleaved boost converter and the conventional hard-switched counterpart are illustrated in Fig. 8. The proposed converter full load efficiency is about 95.1% which is much higher than that of a conventional hard-switched interleaved boost converter with 92.6% efficiency at full load. Fig. 9 exhibits the proposed converter laboratory prototype. Table 2. Comparison of losses in hard switching interleaved boost converter and the proposed converter Proposed converter Conventional hard switching converter switches Vpk, Irms S1, S2 400 V, 0.84 A 400 V, 0.95 A Sa 400 V, 0.84 A NA diodes VF, Iave D1, D2 1 V, 0.12 A 1 V, 0.25 A Da1, Da2 1 V, 0.44 A NA Da3, Da4 1 V, 0.35 A, 0.23 A NA semiconductor components losses, W Sa capacitive turn-on loss 5.6 NA Sa switching loss 0 NA Sa conduction loss 0.38 NA Da1, Da2 conduction loss 2 × 0.44 NA Da3, Da4 conduction loss 0.35, 0.23 NA S1, S2 capacitive turn-on loss 0 2 × 2.8 S1, S2 switching loss 0 2 × 2.57 S1, S2 conduction loss 2 × 0.19 2 × 0.24 D1, D2 conduction loss 2 × 0.125 2 × 0.25 total loss (theoretical) 8.07 11.72 total loss (experimental) 10.3 16.9 Fig. 8Open in figure viewerPowerPoint Efficiency comparison between the proposed ZVT interleaved boost converter and the conventional hard-switched interleaved boost converter Fig. 9Open in figure viewerPowerPoint Laboratory prototype A comprehensive comparison between various features of the proposed converter and some other outstanding counterparts is presented in Table 3. Table 3. Comparison between the proposed converter and other ZVT interleaved boost converters Characteristic [16] [17] [18] [19] Proposed converter operating mode CCM CCM DCM CCM CCM soft switching condition main switches ZVS turn on/off ZVS turn on ZVS turn off ZCS turn on ZVS turn off ZVS turn on ZCS turn off ZVS turn on/off main diodes ZCS turn off ZCS turn off ZCS turn off ZCS turn off ZCS turn off Aux. switch(es) ZCS turn on/off ZCS turn on/off ZCS turn on ZVS turn off hard switched turn on/off ZCS turn on/off Aux. diodes NAa ZCS turn off hard switched turn off hard switched turn off ZCS turn off input current notch yes yes no no no voltage stress main switches Vo Vo Vo Vo Vo main diodes Vo Vo 2Vo Vo Vo current stress main switches IL >2IL >IL IL IL main diodes IL IL IL IL IL extra semiconductor in power path no no yes yes no floating gate drivers 2 2 2 0 0 number of aux. elements switch(es) 2 2 2 1 1 diodes 0a 2 4 3 4 magnetic core(s) 1 2 0 1 2 converter condition Vin (V), Vo (V) Po(max) (W) fsw (kHz) efficiency (%) 14, 42 200 42 95 48, 180 60 20 94.4 18–150, 200 1000 100 96 150 and 250, 400 600 50 94.6 100, 400 200 100 95.1 a May need an extra diode to create the required unidirectional switch. 5 Extending the applications and modifying the ZVT cell The proposed auxiliary circuit can be applied to interleaved buck and interleaved buck–boost converters as shown in Fig. 10. Their operation analysis, design, and soft switching considerations are analogues to that of interleaved boost converter presented in Sections 2 and 3. The number of interleaved phases in the proposed interleaved converters can be increased while using only one auxiliary circuit to accomplish soft switching operation for the semiconductor devices. The number of phases depend on the maximum possible switching frequency of the auxiliary circuit which determines the required transient time intervals to provide soft switching. However, similar to other power electronic converters, the absolute maximum frequency depends on the utilised technology, output power, and the quality of circuit components. Fig. 10Open in figure viewerPowerPoint Other interleaved converters utilising the ZVT cell (a) ZVT interleaved buck converter, (b) ZVT interleave buck–boost converter, (c) Modified ZVT interleaved buck converter The converter metal–oxide–semiconductor field-effect transistors (MOSFETs) exhibited in Fig. 10a are common grounded and do not need floating gate drivers. Nevertheless, this converter application is limited since its input and output grounds are not connected. Hence, as it is indicated in Fig. 10c, the ZVT cell is modified so that it can be applied to typical common input–output ground interleaved buck converters. The operation of this converter is like the converter shown in Fig. 10a. In this converter, the auxiliary switch turns on prior to each main switch turn on, and D1 and D2 currents reduce in resonant manner until these diodes turn off. The resonant current discharges the snubber capacitors and turns on S1 and S2 anti-parallel diodes. Note that in this converter, Da4 prevents Ca voltage to become less than Vin and hence the switch voltage is clamped. In order to reduce the ZVT cell size in the proposed family of ZVT interleaved converters, the auxiliary inductors can be coupled as shown in Fig. 11. The coupling does not negatively affect the voltage and current stresses of the converter semiconductor devices and the operational analysis and converter design basically stay the same as those explained in Sections 2 and 3. The difference in the operation of the ZVT cell in this case is that when the auxiliary switch turns on with coupled inductors, due to the coupling of two windings, a current equal to is induced in La2 and slightly increases the conduction loss in comparison to the original version of the ZVT cell. Fig. 11Open in figure viewerPowerPoint Different interleaved converters utilising the ZVT cell with coupled auxiliary inductors (a) ZVT interleaved buck converter, (b) ZVT interleaved boost converter, (c) ZVT interleaved buck–boost converter 6 Conclusions A family of ZVT interleaved DC/DC converters including boost, buck, and buck–boost types is introduced in this paper. The auxiliary circuit provides soft switching for the multi-phase interleaved converters by using only one active switch. The experimental results of the boost type laboratory prototype operating at 100 kHz and 200 W has verified the theoretical analysis and effectiveness of the proposed method. The main switches of the proposed converter turn on and off under ZVS even at light loads. The main diodes turn off at ZCS and hence, their reverse recovery problem is relieved. Besides, no additional voltage and current stresses are imposed to the main semiconductors. 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