Hetero‐material CPTFET with high‐frequency and linearity analysis for ultra‐low power applications
2018; Institution of Engineering and Technology; Volume: 13; Issue: 11 Linguagem: Inglês
10.1049/mnl.2018.5075
ISSN1750-0443
AutoresDharmendra Singh Yadav, Dheeraj Sharma, Sukeshni Tirkey, Deepak Sharma, Shriya Bajpai, Deepak Soni, Shivendra Yadav, M. Aslam, Neeraj Sharma,
Tópico(s)Integrated Circuits and Semiconductor Failure Analysis
ResumoMicro & Nano LettersVolume 13, Issue 11 p. 1609-1614 Regular PaperFree Access Hetero-material CPTFET with high-frequency and linearity analysis for ultra-low power applications Dharmendra Singh Yadav, Corresponding Author Dharmendra Singh Yadav dharmendra.yadav@iiitdmj.ac.in Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorDheeraj Sharma, Dheeraj Sharma Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorSukeshni Tirkey, Sukeshni Tirkey Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorDeepak Ganesh Sharma, Deepak Ganesh Sharma Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorShriya Bajpai, Shriya Bajpai Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorDeepak Soni, Deepak Soni Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorShivendra Yadav, Shivendra Yadav Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorMohd. Aslam, Mohd. Aslam Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorNeeraj Sharma, Neeraj Sharma Department of Computer Science Engineering, Ramrao Adik Institute of Technology, Nerul, Navi, Mumbai, IndiaSearch for more papers by this author Dharmendra Singh Yadav, Corresponding Author Dharmendra Singh Yadav dharmendra.yadav@iiitdmj.ac.in Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorDheeraj Sharma, Dheeraj Sharma Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorSukeshni Tirkey, Sukeshni Tirkey Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorDeepak Ganesh Sharma, Deepak Ganesh Sharma Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorShriya Bajpai, Shriya Bajpai Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorDeepak Soni, Deepak Soni Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorShivendra Yadav, Shivendra Yadav Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorMohd. Aslam, Mohd. Aslam Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, 482005 Madhya Pradesh, IndiaSearch for more papers by this authorNeeraj Sharma, Neeraj Sharma Department of Computer Science Engineering, Ramrao Adik Institute of Technology, Nerul, Navi, Mumbai, IndiaSearch for more papers by this author First published: 01 November 2018 https://doi.org/10.1049/mnl.2018.5075Citations: 1AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract In this work, the authors have focused on increasing the current driving capability, speed of operation, suppression of parasitic capacitance and ambipolarity of the charge plasma tunnel field effect transistor (CPTFET). Gate dielectric and hetero-material engineering are employed in the CPTFET to obtain better drain current. Introduction of high-k dielectric increases the injection of charge carriers in the intrinsic body while a low-energy bandgap III–V material reduces the tunnelling width leading to the increased rate of band-to-band tunnelling of electrons and thus, enhancing the ON-state current of the device. Hence, the proposed device shows superior performance when operated in regime of DC and high frequency. For reducing the ambipolar conduction in the device, a widely used concept of underlapping of gate electrode is employed which reduces the leakage current in the device. Further, to determine the reliability of the device at high frequency, an analysis of linearity parameters is carried out. The proposed device is highly reliable to function at high-frequency regime. Therefore, the overall introduction of gate dielectric engineering, hetero-material engineering and underlapping of gate electrode improves the performance and characteristics of CPTFET. 1 Introduction In the present era of nano-scale electronic devices, the central idea of semiconductor industries is to focus on developing high-performance device at the affordable price with increased density of transistor in integrated circuits. Metal–oxide–semiconductor field effect transistors (MOSFETs) are considered over conventional bipolar transistor because of its reduced size and better driving current which leads to increased speed of operation. Further, downscaling of traditional MOSFET guided to the matter of short channel effects [[1], [2]]. These effects include variation in the threshold voltage () of the device, drain induced barrier lowering, velocity saturation and increased leakage current [[1], [2]]. Tunnel field effect transistor (TFET) is a device introduced over past few decades and has shown great advantages over traditional MOSFETs because of its unique working mechanism based on the phenomenon of band-to-band tunnelling (BTBT) within energy bands. Subthreshold slope () of MOSFET is restricted to the value of 60 mV/decade as illustrated in (1), whereas TFET provided steeper on–off switching characteristic due to its capability of achieving subthreshold slope () 15 nm, ON-state current in the HGO-HM-CPTFET shows decrement in its value. This is due to shortening of gate electrode which results in loss of its controllability over the channel region, hence affecting the DC as well as high-frequency characteristics of the HGO-HM-CPTFET. From Table 3, it is observed that increase in underlap length reduces the of the device because of shrinking of inversion layer on the drain end of the device. This enhances the switching capability for digital applications without having any influence on the ON-state current. As there is minimal variations in ON-state current, of the device also shows minor variations with the increment in the underlap length. Therefore, the of the device enhances with increased underlap length because of rapidly decreasing and steadily decreasing . GBP of the device also shows similar behaviour as that of . Table 3. High-frequency analysis Parameters Space between gate-drain electrode (UL) 0 nm 5 nm 10 nm 15 nm 20 nm 5.7 5.08 4.25 3.42 6.51 1260 1220 1140 1050 152 72 84.8 95.5 105 22.9 GBP, GHz/µm 16.5 21.9 26.9 31.8 7.42 5 Linearity analysis An assertion is required to obtain minimised distortion of the signal in the present-day communication systems. Along with minimised distortion, the high speed of the device determines its aptness while operating in DC and analogue/RF regime. To get a system with enhanced linearity performance, transconductance () of the device ought to be persistent over a wide range of input signal. However, non-linear behaviour occurs in MOSFETs and TFETs too, because of variations of over input signal [[19]]. The linearity distortion responses like VIP2, VIP3, IIP3 and IMD3 are investigated to counter-balance the effect of non-linearity in the device [[20]] (7) (8) (9) (10) (11) where is utilised majorally in RF applications. The extrapolating input gate voltage is constituted as VIP2 in which a similar first-order harmonic voltage including second-order harmonic voltage is obtained. Identical harmonic voltages of first- and third-order are obtained by the extrapolating input voltage denoted by VIP3. Similarly, the extrapolated input power designated by IIP3 has first- and third-order harmonic powers to be identical. The third-order intermodulation distortion is described by the IMD3 which has the power of intermodulation components of fundamental and third-order are equivalent to one another [[21]]. In order to have a device with lower distortion, the parameters of VIP2, VIP3 and IIP3 need to be high so as to increase the linearity performance while IMD3 needs to be lowered [[20]]. Fig. 7a denotes the comparison of VIP2 with implemented gate-to-source voltage for CPTFET, HGO-CPTFET and HGO-HM-CPTFET. VIP2 is an imperative linearity metrics which resolves the distortion features in the several DC parameters. A large value of VIP2 is preferred for acquiring high linearity and lower distortion performance in the above-mentioned device. It is evident from Fig. 7a that HGO-HM-CPTFET signifies a inflated value of VIP2 in contrast to other devices. This happened because of the incorporation of lower energy bandgap material of GaSb at the source. Fig. 7b illustrates the comparative analysis of VIP3 with regards to applied gate-to-source voltage for devices. It is clear from this figure that a high peak is viewed for HGO-HM-CPTFET as compared to the counterpart of it. Moreover, peak of VIP3 is altered towards lower gate bias which affirms that it is accomplished to attain better linearity. Fig. 7Open in figure viewerPowerPoint Variations of a VIP2 b VIP3 as a function of gate-to-source voltage for CPTFET, HGO-CPTFET and HGO-HM-CPTFET The variation of IIP3 with input gate voltage for proposed devices is demonstrated in Fig. 8a. It clearly reflects a peak is observed in IIP3 for HGO-HM-CPTFET as compared to the latter devices and also the peak is shifted towards lower gate bias which replicates in better linearity and lower distortion. Fig. 8b depicts the change in IMD3 with change in applied gate-to-source voltage. The origination of IMD3 is caused by the non-linearity in the device. This non-linearity is revealed by the static characteristics of transistor which leads to profligacy of signal in wireless system [[19]]. Therefore, it is significant to emphasise that the IIP3 power in Fig. 8a presented by HGO-HM-CPTFET is greater than IMD3 depicted in Fig. 8b, which ensures immunity against hot-carrier effect, and provides improved power, thereby enabling a reduction in intermodulation distortion. Fig. 8Open in figure viewerPowerPoint Variations of a IIP3 b IMD3 as a function of gate-to-source voltage for CPTFET, HGO-CPTFET and HGO-HM-CPTFET 6 Conclusion From above analysis, it is noticed that the increase in the ON-state current of the HGO-HM-CPTFET is due to the contribution of both the lower energy bandgap material of GaSb at the source region and high-k dielectric of HfO2. The proposed device shows better performance at high-frequency regime than conventional Si-based device. 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