Hardware implementation of the quasi‐maximum likelihood estimator core for polynomial phase signals
2018; Institution of Engineering and Technology; Volume: 13; Issue: 2 Linguagem: Inglês
10.1049/iet-cds.2018.5112
ISSN1751-8598
AutoresNevena R. Brnović, Igor Djurović, Veselin N. Ivanović, Marko Simeunović,
Tópico(s)Advanced Electrical Measurement Techniques
ResumoFlexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.
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