High step‐up DC–DC converter using one switch and lower losses for photovoltaic applications
2018; Institution of Engineering and Technology; Volume: 11; Issue: 13 Linguagem: Inglês
10.1049/iet-pel.2018.5400
ISSN1755-4543
AutoresMohammad Maalandish, Seyed Hossein Hosseini, Tohid Jalilzadeh, Naser Vosoughi,
Tópico(s)Multilevel Inverters and Converters
ResumoIET Power ElectronicsVolume 11, Issue 13 p. 2081-2092 Research ArticleFree Access High step-up DC–DC converter using one switch and lower losses for photovoltaic applications Mohammad Maalandish, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorSeyed Hossein Hosseini, Corresponding Author hosseini116j@yahoo.com orcid.org/0000-0002-3716-0126 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorTohid Jalilzadeh, orcid.org/0000-0002-6919-3280 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorNaser Vosoughi, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this author Mohammad Maalandish, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorSeyed Hossein Hosseini, Corresponding Author hosseini116j@yahoo.com orcid.org/0000-0002-3716-0126 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorTohid Jalilzadeh, orcid.org/0000-0002-6919-3280 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorNaser Vosoughi, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this author First published: 03 September 2018 https://doi.org/10.1049/iet-pel.2018.5400Citations: 16AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat Abstract In this study, a new non-isolated high step-up dc–dc converter using one switch and low-voltage stress on semiconductors is presented for photovoltaic applications. The proposed converter consists of one switch in the input side (S), voltage multiplier units (D–C–L), one diode in the output side (Do) and one capacitor (Co). To achieve high-voltage gain and power level, the proposed converter can be extended to n stages of voltage multiplier units. Hence, the output voltage level will be reasonably increased and the nominal value of power devices will be decreased. Therefore, the voltage stress across the power switch is decreasing for different duty cycles at high power levels. As a result, the efficiency of the proposed converter can be increased by using one switch with lower resistance rDS(on). To verify the carried mathematical analysis of the proposed converter and circuit implementation are validated through both the simulation and experimental results that accordance each other well. The experimental results of two prototypes (with n = 2, 3) in about 290 W operating at 33 kHz are provided. 1 Introduction High step-up dc–dc converters have been used in many applications such as photovoltaic (PV) systems, uninterruptible power supply, fuel cell power conversion systems, hybrid PV/FC/battery power system and so on that require high-voltage transfer gain to meet load high voltage [1-4]. Since the output voltage of renewable systems is low, so this aim, high-voltage gain and high-efficiency dc–dc converters are used to overcome the mentioned limitations. Moreover, the input current ripple of dc–dc converters should be low which causes the lifetime of renewable energy to be increased. Usually, an input filter is inserted at the input side for solving this issue [5]. The output voltage of the renewable sources is low and is not steady and cannot be directly connected to the load. For applications that need a steady dc voltage, the buck–boost and boost dc–dc converter is required. In fact, the proposal of these converters is to solve the problem of interference between buck and boost switches performance [6-10]. The traditional buck–boost converter is not suitable for renewable sources. The efficiency of the traditional buck–boost converter is expected high; however, it is low and is limited by the effects of diodes, switches (the normalised voltage across on semiconductors is high) and equivalent series resistance (ESR) of capacitors and inductors [11]. Converters using switching voltage multiplier technique with low-voltage stress across semiconductors have been proposed in [12]. In addition, using a lower voltage and rDS(on) switch in order to reduce cost, switch conduction losses and overall power losses. The quadratic boost converter using a single active switch is another interesting structure for extending the voltage gain [13], where the voltage conversion ratio is given as a quadratic function of the duty cycle. However, the voltage conversion ratio of this converter is moderate since the output voltage level is determined only by the duty cycle. Hence, in high-output voltage applications, a high-voltage rating switch should be selected. Therefore, these converters are not suitable for high step-up voltage conversion ratio in renewable energy applications [14, 15]. In [16], a single switch boost dc–dc converter using diode-capacitor cell is presented. This converter during the operational process of the capacitors is not shortened by the switch and so the large discharge current stresses do not influence the circuit. However, the normalised voltage stress across power switch is high, and as a result the cost of the circuit is high. Many single switch structures based on the conventional boost converter has been presented for high step-up voltage gain. Some of these converters are able to solve the power losses problem of the power switch, and it can obtain the target of high-efficiency and high-voltage conversion ratio [17-19]. In [20, 21], several switching capacitor/switching inductor structures are proposed, and transformer-less hybrid dc–dc converters integrated with classical single switch non-isolated converters. These papers introduce the use of the voltage multiplier unit applied to the classical dc–dc boost topologies in order to obtain high-voltage conversion ratio along with the reduction of the normalised voltage across the switch. The advantages of these converters are such as the energy in the magnetic elements is low, which causes to weight, size and cost saving for the inductor, and fewer conduction losses. In this paper, a new non-isolated high step-up dc–dc converter is presented with different power ranges suitable for renewable applications. The proposed converter uses voltage multiplier units to increase the voltage conversion ratio and reduce the normalised voltage stress across power semiconductors (by decreasing the nominal value of the power devices). The voltage conversion ratio of the proposed converter is higher than the traditional boost converter, SEPIC and ZETA converters. The proposed converter uses one switch; hence, the control of the converter is simplicity. The operation modes of the proposed converter are analysed in Section 2. The experimental and the simulation results are provided to verify the operation of the proposed converter. Power systems computer-aided design/electro-magnetic transient design and control (PSCAD/EMTDC) software is used for simulation work. 2 Proposed converter and principle of operation Fig. 1a illustrates the power circuit of the proposed topology. The proposed topology is a buck–boost dc–dc converter which consists of the input dc voltage source; only one switch in input side and voltage multiplier units (consists of several capacitors, diodes and inductors). For simplicity of the operation analysis of the proposed converter, the below assumptions are considered: The value of input voltage is constant. All used elements of the proposed converter are ideal. All capacitors of the proposed converter are large enough, so the voltage of all capacitors considered constant values in one switching period. Fig. 1Open in figure viewerPowerPoint Proposed converter and principle of operation (a) Power circuit of the proposed structure, (b) Mode 1, (c) Mode 2, (d) Voltage multiplier unit Fig. 1a illustrates the circuit of the proposed converter which is presented for renewable applications. Operation of the proposed converter is shown in Figs. 1b and c. In Fig. 1b, the power switch is on and all inductors have attracted their energy through the input power supply (Vi). In Fig. 1c, the stored energy of all inductors transferred to their capacitors is existed in their voltage multiplier units. Fig. 1d illustrates the circuit of the voltage multiplier unit which is presented in this paper. Fig. 2 illustrates the main waveforms of the proposed converter in continuous conduction mode (CCM) operation. Fig. 2Open in figure viewerPowerPoint Main waveforms of the proposed converter at CCM operation To the analysis of the proposed converter, each switching period of the proposed converter (TS) for each switch can be considered two time. In the first time (DTS), the switch is on-state and the second time [(1 − D)TS], the switch is off-state. 2.1 CCM operation Figs. 1b and c show the equivalent circuit of the proposed converter in CCM operation. On the basis of these figures, we have as follows. 2.2 Mode 1 [0 ≤ t ≤ DTs] In this mode, the power switch (S) is turned on and all diodes are turned on, except the diode Do in output side. The inductor L1 is charged by the input voltage source (Vi) and the current of all inductors (L1, L2, L3, … , Ln+1) is linearly increased. By noting the equivalent of this mode, we have (1) (2) (3) (4) (5) (6) 2.3 Mode 2 [DTs ≤ t ≤ Ts] In this mode, the power switch is turned off and all diodes are turned off, except the diode Do in output side. The current of all inductors (L1, L2, … , Ln, Ln+1) is linearly decreased. The capacitors C1, C2, … , Cn are charged by the capacitors , respectively. The capacitors C1, C2, … , Cn are charged by the inductors L2, L3, … , Ln+1, respectively, and finally the capacitors Co1 and Co2 are charged by the inductor Ln+1. By noting the equivalent of this mode, we have (7) (8) (9) (10) (11) (12) (13)By applying the volt-second law to inductors L1, L2, … , Ln+1 (the inductor average voltage is zero in one period). Using (1)–(4) and (7)–(9), the voltage across the capacitors can be expressed as follows: (14) (15)Using (13)–(15), the voltage conversion ratio of the proposed converter (M) in CCM operation can be expressed by (16) 2.4 Calculation of the current of components 2.4.1 Calculation with switch-on state On the basis of Fig. 1b, we have (17) (18) (19) (20) (21) (22) 2.4.2 Calculation with switch-off state On the basis of Fig. 1c, we have (23) (24) (25)The average current of the diodes when the switch is in on-state can be expressed by (26)Generally, by applying the current-second law on capacitors (the capacitor average current is zero in one period) and using Fig. 1a can be said that the average output current (Io) is equal to IDo. Using the average current law on diodes in one period, the average current on diodes Do1 and Do2 is equal to IDo. In fact, the average current on diodes Do1 and Do2 is equal to Io when the power switch is in on-state. Hence, the average current on diodes Do1 and Do2 can be obtained as follows: (27)By substituting (17) and (21) into (23) and (25), the average current of the inductors can be obtained as follows: (28) (29)Using (16), the current ripple of the inductors can be obtained as follows: (30) 2.5 Discontinuous conduction mode operation The principle operation of the proposed converter in discontinuous conduction mode (DCM) operation is described in this section. The proposed converter consists of three modes of DCM operation. The first mode is the same in CCM operation and DCM operation. In the second mode, the current of all diodes earlier will be zero compared with CCM operation. Hence, in the third mode, the switch S and all diodes will be turned off. The equivalent circuit of the proposed converter in the third mode and the main waveforms in DCM operation are shown in Fig. 3. Fig. 3Open in figure viewerPowerPoint Equivalent circuit of the proposed converter in the third mode and the main waveforms in DCM operation (a) Main waveforms of the proposed converter at DCM operation, (b) Mode 3 Using (21) and (24), the sum of the diodes average current can be obtained as follows: (31)On the basis of Fig. 1c for the diodes’ average current in one period switching can be expressed by (32) (33)The sum of the peak current of all inductors is (34) (35)By applying the volt-second law on all inductors, it can be achieved as follows: (36)Using (35) and (36), the conversion voltage ratio in DCM can be expressed by (37) 3 Analysing the switch voltage stress, efficiency and maximum power point tracking (MPPT) of the proposed converter 3.1 Analysis of the voltage stress across the switch With regarding Fig. 1c, the voltage stress across the power switch (S) of the proposed converter can be achieved by (38)Using (14)–(16) and (38), the normalised voltage stress across the switch (S) versus different duty cycles can be expressed by (39) 3.2 Calculation of the efficiency of the proposed converter For calculation of the efficiency of the proposed converter , the parasitic resistances of components are defined as follows: rDS-on→ on-state resistances of the switch S; RL1, rL2, … , rLn, rL(n+1)→ are the ESRs of inductors L1, L2, … , Ln and Ln+1; rD1, rD2, … , rDn, rDo→ are the ESRs of diodes D1, D2, … , Dn and Do; and rC1, rC2, … , rCn, rCo→ are the ESRs of capacitors C1, C2, … , Cn and Co. The power loss of the switch (S) can be achieved as follows: (40)Using (28) and (29), the conduction losses of the inductors L1, L2, … , Ln and Ln + 1 can be achieved as follows: (41)Using (26), the forward resistance losses and voltage losses of the diodes D1, D2, … , Dn, Do1, Do2 and Do can be achieved as follows: (42)The power losses of the capacitors C1, C2, … , Cn and Co can be achieved as follows: (43)Using (40)–(43), the overall efficiency of the proposed converter can be achieved as follows: (44) 3.3 Dynamic performance and control method To analyse the dynamic performance of the proposed converter, the state-space averaging method is used for achieving an average model of the proposed converter. The system equations are achieved for all operation states, and also they are averaged during one period by taking into account the time interval of each state. To obtain the state equations, the following assumptions are considered: Power switch and all diodes are considered ideal. The input voltage source is constant. All inductors have an equal value L1 = L2 = L3 = L4 = L with parasitic series resistors rL. All capacitors have an equal value with parasitic series resistors rC. In these conditions, there are 13 state variables. The state variables vector is defined as follows: (45) In the first operation mode, the state and output equations and the associated matrixes are given in (46)–(49), where u = Vi (46)In the second operation mode, the state and output equations and the associated matrixes are given in (50)–(52) where u = Vi and the response is the output voltage Vo (47) (48) (51) (52)Dynamic performance of the proposed converter is analysed with the small-signal frequency response. For easy analysis of the proposed converter in this section, all inductors are considered and all capacitors are considered . The magnitude (dB) and phase frequency response of the simulated converter with n = 2,3 are presented in Fig. 4a. Fig. 4b illustrates the closed-loop small-signal transfer function from the output voltage to the duty cycle. A proportional–integral (PI) controller is used to control the output voltage of the proposed converter. The output voltage of the proposed converter is compared with the desired amount of the output voltage (Vo, ref). If there is a difference between the output voltage and Vo, ref, it is applied to the controller to produce a desirable duty cycle. The desirable duty cycle is compared with a carrier wave, and then the proper interpolated pulse is produced to the switch. The PI controller has a gain and time constant that the amount of them is obtained by a trade-off. Fig. 4Open in figure viewerPowerPoint Magnitude (dB) and phase frequency response of the simulated converter (a) Bode plot of the small-signal transfer function from the output voltage to the duty cycle, (b) Closed-loop step response for the proposed two-stage converter due to a step change in input voltage Vi 3.4 Maximuim PPT The rate of variation of PV generator power versus its voltage is given by (53)The slope of the power-voltage curve of a PV module as shown in Fig. 5 is either positive, negative or zero. It is positive on the left of MPP, negative on the right MPP and zeroes at MPP. Accordingly, the relation between the incremental and instantaneous conductances could be given by (54) Fig. 5Open in figure viewerPowerPoint Current IPV versus the voltage VPV of the PV simulator Equation (54) suggests a simple approach for tracking MPP based on continuously comparing the incremental and instantaneous conductance. The PV generator voltage and/or current are then incrementing/decrementing until MPP is reached. This technique is reported in the literature under the incremental conductance controller [22]. Since the sum of the incremental and instantaneous conductance is equal to zero at MPP; therefore, employing a sufficiently fast PI controller ensures that sum is settled at zero. Fig. 5 illustrates the current IPV versus the voltage VPV of the PV simulator (55) 4 Comparison study 4.1 Voltage conversion ratio versus duty cycle Fig. 6a illustrates the relationship between the voltage conversion ratio of the proposed converter and duty cycle with other structures. With regard to Fig. 6, the voltage gain of the proposed converter is higher than other structures. The conversion ratio of the proposed converter will be increased by raising the n number (voltage multiplier unit). In addition, the voltage gain of the proposed converter with large n number is high for lower duty-cycle values [23-25]. Also, the nominal values on semiconductors will be decreased due to the increase of multiplier voltage units in the proposed converter. Fig. 6Open in figure viewerPowerPoint Comparison of the proposed structure with other structures (a) Voltage conversion ratio versus duty cycle, (b) Normalised voltage stress on switch versus duty cycle, (c) Normalised voltage stress on diodes versus duty cycle 4.2 Normalised voltage stress on switches Fig. 6b illustrates the comparison between the normalised voltage stress across switches and different duty cycles. The results obtained from the preliminary analysis of the proposed converter are shown in Table 1, and it can be said the normalised voltage stress across the switch of the proposed converter will be decreased by increasing the n number [30, 31] and [5, 29]. Therefore, the switch of the proposed converter can be used with lower cost for differences in power levels; also, the overall cost of the proposed converter will be reduced. Finally, the efficiency values of the proposed converter will be increased. Table 1. Comparison between the proposed converter and the other structures High step-up converter Voltage gain Normalised voltage stress of switch Diodes normalised voltage stress Input current ripple, % Total device number Switches number Efficiency, % [16] — 4n + 4 1 — [17] 0.5 0.5 — 10 1 95.8 [21] — 4n + 4 2 95 [23] 49 12 1 97.3 [26] 54 12 1 92 [27] — 4n + 8 2 78 [28] 30 8 1 — [29] — 8 1 97.75 [5] 44 12 1 93.5 proposed converter 38 3n + 6 1 95.52 4.3 Normalised voltage stress on diodes Data Fig. 6c can be compared with the data in Table 1 which shows the maximum voltage stress across diodes is lower than other structures for and it is higher than some other structures for n = 1, 2. The normalised voltage stress across diodes of proposed converter approaches to 0.25 for n = 3 and will be reduced by increasing the n number. Generally, but not always, the normalised voltage across diodes of the proposed converter is lower than other structures (except the structure in [5]) [26-28] and [32]. However, the voltage conversion ratio and normalised voltage of the structure in [5] are lower than the proposed converter that shows in Figs. 6a and b, respectively. The differences between the proposed structure and other structures are highlighted in Table 1. It is clear that by increasing the duty-cycle value, the normalised voltage stress across the switch and diodes will be decreased. Therefore, the power losses of the proposed converter will be lower for high power levels. The total device number of the proposed converter is about lower than other structures, generally (total device number of the proposed converter equal to n + 4, while n is the voltage multiplier unit). There is only one switch of the proposed converter that leads to reducing the overall cost of the circuit. Hence, the power losses of the proposed converter will be fewer and the efficiency of the proposed converter will be higher. Using (30), the input current ripple of the proposed converter will be decreased by increasing the voltage multiplier stages. The input current ripple just compared with structures that have a switch in the input side. 5 Simulation and experimental results To verify the theoretical analysis, the proposed converter is simulated in PSCAD/EMTDC comprehensive and the experimental prototypes (with n = 2 and 3) at CCM operation are built and tested. The component characteristics of the simulation study are provided in Table 2. Table 2. Component characteristics of the proposed converter input voltage 24 V switching frequency 33 kHz inductor L1 1 mH inductors L2, L3, … , Ln + 1 all capacitors capacitor Co power switch 2SK3131 all diodes MUR 1560 The experimental prototypes of the proposed converter with n = 2, 3 are shown in Fig. 7. Fig. 7Open in figure viewerPowerPoint Experimental prototype of the proposed converter with n = 2, 3 The experimental results of the proposed converter with n = 2, 3 are summarised in Table 3 that match each other, reasonably well. Table 3. Comparison between the experimental results of the converter with n = 2, 3 Components n = 2 n = 3 Simulation Experiment Simulation Experiment peak voltage on S, V 80.1 80.3 80 79.9 average current S, A 1.46 1.50 12.20 12.31 RMS current S, A 13.01 13.08 16.83 16.95 peak voltage on D1, V 79.1 79.2 78.9 79 average current D1, A 1.46 1.47 1.69 1.74 RMS current D1, A 1.73 1.76 2.08 2.16 To further discuss the verification of the mathematical analysis, the power circuit of Fig. 1a for n = 2, 3 was built and tested. Fig. 8 illustrates the simulated and experimental waveforms of the proposed converter in CCM operation for D = 0.7 value (for n = 2). Fig. 8a illustrates the output voltage (Vo) which is 146.1 V. On the basis of (16), the output voltage of the proposed topology with n = 2 is matched with simulation results. Figs. 8b and c illustrate the current waveforms of the inductors L1 and L2. According to Fig. 8b, the average current of the inductor L1 is about 7.78 A that is confirmed to (28). The ripple of the current inductor L1 is about 6.5% that is obtained in (31). According to Fig. 8c, the average current of the inductor L2 is about 1.47 A that is obtained in (29). The ripple of the current inductor L2 is about 59% that is obtained in (29). The current of inductor L3 waveform is not shown since it is similar to inductor L2 current waveform. Fig. 8d illustrates the value of the maximum voltage across power switch S that is about 80.1 V and this value conforms with (38) reasonably well. Fig. 8e illustrates the maximum voltage stress across diode D1 that is about 79.1 V, also this value conforms to the mathematical results. The voltage of the diode D2 waveform is not shown since it is similar to the diode D1 voltage waveform. The maximum voltage stress value across diodes Do1 and Do2 are similar diodes D1 and D2, but they complement forward each other. Fig. 8Open in figure viewerPowerPoint Simulated and experimental waveforms of the proposed converter in CCM operation with n = 2 (a) Output voltage, (b) Current inductor L1, (c) Current inductor L2, (d) Voltage across power switch S, (e) Voltage stress across diode D1 Fig. 9 illustrates the simulated and experimental waveforms of the proposed converter in CCM operation for D = 0.7 value (for n = 3). Fig. 9a illustrates the output voltage (Vo) which is 168.3 V. On the basis of (16), the output voltage of the proposed topology with n = 2 matches with simulation results. Figs. 9b and c illustrate the current waveforms of the inductors L1 and L2. According to Fig. 9b, the average current of the inductor L1 is about 10.66 A that it is confirmed to (28). The ripple of the current inductor L1 is about 4.7% that is obtained in (30). According to Fig. 9c, the average current of the inductor L2 is about 1.68 A that is obtained in (29). The ripple of the current inductor L2 is about 52% that is obtained in (30). The current of inductors L3 and L4 waveforms are not shown since these are similar to inductor L2 current waveform. Fig. 9d illustrates the value of the maximum voltage across power switch S that is about 80 V and this value conforms with (38) reasonably well. Fig. 9e illustrates the maximum voltage stress across diode D1 that is about 78.9 V, also this value conforms to the mathematical results. The voltages of diodes D2 and D3 waveforms are not shown since these are similar to diode D1 voltage waveform. The maximum voltage stress value across diodes Do1 and Do2 are similar diodes D1, D2 and D3, but they complement forward each other. Fig. 9Open in figure viewerPowerPoint Simulated and experimental waveforms of the proposed converter in CCM operation with n = 3 (a) Output voltage, (b) Current inductor L1, (c) Current inductor L2, (d) Voltage across power switch S, (e) Voltage stress across diode D1 Fig. 10 illustrates the efficiency of the proposed converter for D = 0.7. According to Fig. 10a, the maximum efficiency of the proposed converter (95.6%) is obtained at about Po = 164 W and the efficiency of the proposed converter is about 95.1% at Po = 290 W which these values obtained for the prototype n = 2. According to Fig. 10b, the maximum efficiency of the proposed converter 95.6% obtained at about Po = 260 W and the efficiency of proposed converter is about 95.52% at Po = 290 W that this value obtained for the prototype n = 3. By considering these figures, the efficiency of the proposed converter for 400 W limits is 1.6% tolerances. By increasing the voltage multiplier units, the output voltage and output current are increased, so the output power level will be increased. The efficiency of the proposed converter at all power levels is higher than 92%. Therefore, the overall efficiency of the proposed converter is between 92 and 95.6%. As a result, it causes the efficiency of the proposed converter improvement for the same power. Fig. 10Open in figure viewerPowerPoint Efficiency of the proposed converter for different power levels (a) n = 2, (b) n = 3 The transient response of the output voltage in response to a step change (40%) in input voltage is shown in Fig. 11a. It can be observed from Fig. 11a that the variation of the output voltage is about 4% with a 40% changes in the input voltage value for n = 2. The variation of the output voltage is about 3.6% for n = 3 shown in Fig. 11b (the input voltage have increased 40% for n = 2, 3). Fig. 11Open in figure viewerPowerPoint Closed-loop step response for the proposed two-stage converter with 40% changes in the input voltage Vi (a) n = 2, (b) n = 3 6 Conclusions In this paper, a new high step-up dc–dc converter with lower losses for renewable energy applications is presented. The proposed converter only has a single switch in the input side; hence, the power losses will be low. In addition, the control of the proposed converter is simplicity and the resistance of power switch for on-state is low. To obtain high-voltage gain, the proposed converter can be extended to n stages of voltage multiplier units (D–C–L), so the output power level will reasonably increase. As a result, by decreasing the nominal value of components, the voltage stress of power switch and diodes is decreased at different duty cycles. The experimental results of two prototypes rated 290 W operating at 33 kHz are provided. Therefore, the proposed converter can be useful in many applications such as PV applications. The maximum efficiency of the proposed converter is about 95.52% at Po = 290 W. The simulation and experimental results illustrate that the proposed converter achieves the low-voltage stress of power switch, low-voltage stress of diodes and the overall efficiency higher than about 92% in all power limits. 7 References 1Babaei E., Mahmoodieh M.E.S., and Mahery H.M.: ‘ Operational modes and output-voltage-ripple analysis and design considerations of buck–boost DC–DC converters’, IEEE Trans. Ind. Electron., 2012, 59, (1), pp. 381– 391CrossrefWeb of Science®Google Scholar 2Mahery H.M., and Babaei E.: ‘ Mathematical modeling of buck–boost dc–dc converter and investigation of converter elements on transient and steady state responses’, Int. J. Electr. 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