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Low power aware pulse triggered flip flops using modified clock gating approaches

2018; Emerald Publishing Limited; Volume: 15; Issue: 6 Linguagem: Inglês

10.1108/wje-09-2017-0309

2515-8082

Sudhakar Jyothula,

Semiconductor materials and devices

Purpose The purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF). Design/methodology/approach In the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved. Findings The design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity. Originality/value The study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.