Fast digital foreground gain error calibration for pipelined ADC
2018; Institution of Engineering and Technology; Volume: 13; Issue: 2 Linguagem: Inglês
10.1049/iet-cds.2018.5230
ISSN1751-8598
AutoresJupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal,
Tópico(s)Advancements in PLL and VCO Technologies
ResumoIET Circuits, Devices & SystemsVolume 13, Issue 2 p. 219-225 Research ArticleFree Access Fast digital foreground gain error calibration for pipelined ADC Jupinder Kaur, Jupinder Kaur Bombardier Transportation India, Vadodara, Gujarat, IndiaSearch for more papers by this authorPrince Prabhakar, Prince Prabhakar Electronics and Communication Engineering Department, Thapar University, Patiala, IndiaSearch for more papers by this authorAnil Singh, Corresponding Author Anil Singh anils.rawat@thapar.edu Electronics and Communication Engineering Department, Thapar University, Patiala, IndiaSearch for more papers by this authorAlpana Agarwal, Alpana Agarwal Electronics and Communication Engineering Department, Thapar University, Patiala, IndiaSearch for more papers by this author Jupinder Kaur, Jupinder Kaur Bombardier Transportation India, Vadodara, Gujarat, IndiaSearch for more papers by this authorPrince Prabhakar, Prince Prabhakar Electronics and Communication Engineering Department, Thapar University, Patiala, IndiaSearch for more papers by this authorAnil Singh, Corresponding Author Anil Singh anils.rawat@thapar.edu Electronics and Communication Engineering Department, Thapar University, Patiala, IndiaSearch for more papers by this authorAlpana Agarwal, Alpana Agarwal Electronics and Communication Engineering Department, Thapar University, Patiala, IndiaSearch for more papers by this author First published: 18 February 2019 https://doi.org/10.1049/iet-cds.2018.5230Citations: 1AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue-to-digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix-7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non-linearity improves by 30% and integral non-linearity reduces from values +60/−60 LSB to +0.77/–0.77 LSB. Also, signal to noise and distortion ratio and spurious-free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration. 1 Introduction The pipelined analogue-to-digital converter (ADC) is widely used in modern communication applications, especially in radar, aerospace, and automotive systems for its better trade-off between resolution and conversion speed [1]. However, the ADC's resolution is mainly limited by the negative effects such as gain error of operational amplifier (op-amp), op-amp's incomplete settling, its non-linearity, and capacitance mismatch [2, 3]. By designing a robust op-amp, such non-idealities can be overcome but at the cost of an increase in area and power in the ADC. Therefore, to save the area and power, calibration techniques are applied as a preferred design approach. Usually, there are analogue and digital methods of calibration to compensate the pipelined ADC errors. Analogue methods, such as error averaging [4], commutated feedback capacitor switching (CFCS) [5], and reference feed-forward technique [6], consume more power and area with complicated circuitry. Therefore, digital methods have been exploited because of their flexibility and scaling benefits. The later approach estimates and calibrates the ADC's non-idealities in the digital domain. According to whether ADC's operation is interrupted or not, digital calibration is divided into foreground calibration and background calibration, respectively. Background calibration technique detects and calibrates the pipelined ADC by using a reference ADC [7-12] or by applying some uncorrelated random sequence [13, 14], while the ADC is continuously working. However, this technique lacks in precision estimations and takes thousands of cycles to calibrate. On the other hand, foreground calibration technique extracts the stage error by comparing the actual output response of a test signal and ideal code, and then whole ADC is calibrated when it is interrupted [15, 16]. For an op-amp-less pipelined ADC, a boosted charge transfer (BCT) circuit with replica calibration is presented in [17] that uses negative feedback network inside the replica circuit of the BCT to calibrate the ADC. This paper proposes a fast digital foreground calibration technique to compensate the gain error due to low open-loop gain of op-amp with the help of least mean squares (LMS) algorithm. Unlike the earlier published work [7-12], this work does not require a slow but accurate reference ADC to calibrate the pipelined ADC, thus save the area, speed, power, and design efforts required in designing a pipelined ADC. Section 2 discusses the various non-idealities in a pipelined ADC. Section 3 describes the proposed foreground digital calibration, and its implementation and simulation results are presented in Section 4. Finally, conclusion is given in Section 5. 2 Non-idealities analysis of pipelined ADC Fig. 1 shows a fully differential op-amp-based 1.5-bit pipelined ADC stage. Ideally, the residue voltage of the pipelined ADC stage is given by , where and represent the input voltage and sub-DAC output of the pipelined ADC stage, respectively. However, in reality, a stage may suffer from various non-idealities such as low open-loop gain of op-amp, incomplete settling, and capacitor mismatch. These errors deviate the interstage gain (G) from its ideal value of 2 and results in erroneous residue voltage as given by [18] (1) Fig. 1Open in figure viewerPowerPoint Op-amp-based fully differential 1.5-bit pipelined ADC stage Here, A is the open-loop gain, UGB the unity gain bandwidth of op-amp, β the feedback factor, and represents the capacitor mismatch error. To avoid the stage error, unity gain bandwidth should be large, so that . Also, capacitors Cs and Cf should be perfectly matched, so that . If Cs and Cf are not perfectly matched, it causes deviation of stage gain from its ideal value of 2. Parasitic capacitance Cp at the input of op-amp (as shown in Fig. 1) further adds to gain error. Also, open-loop gain A of op-amp is required to large enough, so that and hence, . All these factors deviate the stage gain from its ideal value of 2 and calibration is performed to calibrate pipelined ADC for one or more of these errors [7-9, 13-16, 19]. Gain error occurs due to low open-loop gain of op-amp and causes the missing codes in ADC transfer function, i.e. non-linearity is introduced. The extent of non-linearity [measured in terms of differential non-linearity (DNL) and integral non-linearity (INL) increases with increase in gain error. This work focuses on the problem of gain error correction in 1.5-bit/stage pipelined ADC architecture using a digital calibration technique that can also be extended to other multi-bit pipelined ADC architectures. Fig. 2a shows residue voltage of the first stage with op-amp gain of 40 V/V. Fig. 2b shows the effect of gain error on second-stage residue, when op-amp open-loop gain in both, first and second, stage is 40 V/V. Fig. 3 shows the output of 12-bit pipelined ADC using such a low-gain op-amp in its first stage with all the remaining stages assumed ideal. It shows the missing codes at the ADC output. For no missing codes, the required open-loop gain of the first-stage op-amp is 4096 V/V [18]. Achieving such a high gain would require more area and power. As a solution of this, a novel fast digital foreground method for calibration is developed and applied in a 12-bit pipelined ADC with 1.5-bit/stage architecture to show its effectiveness. The proposed calibration technique is discussed in Section 3. Fig. 2Open in figure viewerPowerPoint Effect of gain error on residue plot of(a) First stage, (b) Second-stage pipelined ADC Fig. 3Open in figure viewerPowerPoint Transfer function of a 12-bit 1.5-bit per stage pipelined ADC with gain error 3 Proposed digital foreground calibration The digital output of a 12-bit pipelined ADC can be written as [15] (2) where is the weight of stage i with as the output of sub-ADC block (shown in Fig. 1). Here, represents the decimal equivalent of the binary value with −1, 0, or 1 corresponding to as 00, 01, or 10, respectively. Ideally, is equal to 0.5 (i.e. with in ideal case), whereas in the case of a non-ideal stage, is different from 0.5 [as shown in (1)] and requires a calibration algorithm to find out the estimates of the weights. Fig. 4 illustrates the 12-bit pipelined ADC with the proposed digital calibration logic. The proposed method is built over the calibration schemes discussed in [7-12, 19-23]. An ideal 12-bit pipelined ADC comprises ten 1.5-bit/stage pipelined stages and one 2-bit flash ADC at the end. However, due to low open-loop gain of op-amp, G reduces from its ideal value of 2 and therefore, extra stages are required to achieve the 12-bit linearity. In this work, the open-loop gain of op-amp is 40 V/V, causing G to reduce from 2 to ∼1.90. Therefore, to achieve 12-bit linearity, it requires 11 1.5-bit/stage pipelined stages with one 2-bit flash ADC at the end. Redundancy removal block shown in Fig. 4 takes care of the comparator offset in the sub-ADC block up to the range of . Fig. 4Open in figure viewerPowerPoint Proposed digital foreground calibration technique Fig. 5Open in figure viewerPowerPoint Convergence of weight (w1) of the first pipelined stage for different values of step size (µ) As shown in Fig. 4, two extra pipelined stages are cascaded before the 2-bit flash ADC only for calibration purpose and are assumed to be ideal with G equal to 2. These three stages – two extra pipelined stages for calibration and 2-bit flash stage –together form an ideal back-end ADC. Thus, complete pipelined ADC consists of 14 stages, out of which stages 12 and 13 are used only during the calibration process. Once the calibration is complete, these two extra stages are removed from the pipelined ADC to do its normal operation. Stages 1–11 need to be calibrated one by one starting with stage 11. After a stage is calibrated, it is considered to be a part of ideal back-end ADC for next iteration. Thus, while calibrating the stage i, stages from to the last stage form an ideal back-end ADC or more precisely calibrated back-end ADC. In the proposed calibration scheme, the stage to be calibrated (say stage i) is given an input voltage which is kept at high-level ADC reference voltage . For the proposed calibration to work, is converted into floating point representation (represented by ) and stored in the memory as a constant. Unlike earlier work published in [7-12], here, an accurate reference ADC to generate the expected value is not required. It, therefore, reduces the area, power, and design effort required in designing a reference ADC and further reduces the overall area and power in the pipelined ADC. Also, the time required to calibrate the pipelined ADC is much less when compared with earlier work [7, 8, 10-12], where the calibration speed is mainly limited by the speed of reference ADC which remains much slower when compared with the pipelined ADC. Another advantage of using as calibration input is that maximum error is found at full-scale voltage. Calibrating the ADC against maximum error brings it closer to ideal, when compared with calibrating against lesser error values. Fig. 4 represents calibration of stage i in 12-bit pipelined ADC. Calibration input generates two output bits and residue voltage according to (3). Here, and only gain error is considered (3) This residue voltage is fed as input to the next stage , which generates residue voltage to be used as input to stage , and so on. After each stage (from stage i to stage 14) has generated two bits, all these bits are sent to redundancy removal block. For stage i, bits from to are used to generate decimal equivalent of back-end voltage as (4) where N is the number of stages in pipelined ADC to be calibrated (in Fig. 4, ) and represents the weight of already calibrated stage . It is to be noted here that factor if ; otherwise, it is if and represented as in Fig. 4. Two extra pipelined stages added for calibration purpose are assumed to be ideal here. Adding extra stages increases the resolution of back-end ADC and reduces the quantisation noise. However, if the similar 1.5-bit stages with gain error (non-ideal case) are used, the proposed calibration will still work since conversion error at the output of stage 11 is smaller than the LSB of back-end ADC comprising stages 12–14 with little increase in the number of calibration clock cycles. shown in Fig. 4 represents the decimal equivalent of analogue input applied to the ADC formed by uncalibrated stage i and calibrated back-end ADC. is calculated as (5) This value is then subtracted from to obtain the error according to the following equation (6) and are then passed to calibration logic comprising LMS adaptive algorithm, in order to calculate the new value of weight (7) Here, μ is the step size. It acts as a factor to adjust the convergence speed of the algorithm. Here, even if µ is set to unity, it still updates with a sufficiently small value. Keeping µ = 1 gives the advantage of reducing the number of multiplications as clear from the last term in (7) and therefore makes the algorithm faster. Fig. 5 shows the updation of weight for different values of µ. With new value of , (4)–(7) are repeated unless lesser than LSB/4 is obtained. Once correct value of is obtained, i is decremented and the corresponding stage is calibrated next. This goes on until all the stages get calibrated. In this work, all the decimal numbers are represented in single precision (i.e. 32-bit) IEEE standard-754 for floating point representation. The algorithm is presented in the form of a flowchart in Fig. 6. Every time calibration has to take place, ADC has to be given calibration input voltage . Calibration starts from the last non-ideal stage and move towards the front stage after calibrating the stages one-by-one. Fig. 6Open in figure viewerPowerPoint Flowchart representing the proposed LMS-based calibration algorithm 4 Hardware implementation The calibration logic is implemented in Xilinx Artix-7 FPGA using Verilog HDL as a finite state machine (FSM). The input to the calibration module is a clock signal of 100 MHz and a reset signal. The output is new weight after calibration, and a flag indicates the availability of correct weight at output, i.e. marks the completion of calibration. As discussed earlier, the value of is stored in the memory (available in the FPGA) as a floating point value and defined by and used in calculating the value of error after giving the calibration input . Output bits obtained from pipelined ADC are also stored in the memory. In the case of 12-bit pipelined ADC, when , 5 bits are obtained; for , 6 bits are obtained, and so on. Thus, a total of bits are obtained for 12-bit pipelined ADC. All the weights to are initialised with an initial value of 0.5 and stored in memory, which are read as well as updated during the calibration process. Dedicated DSP cores available in Artix-7 FPGA are used for floating point calculations which makes the algorithm power–area–speed efficient [24]. Otherwise, it would utilise more core area and power to implement the floating point arithmetic functionality. Fig. 7 shows the block diagram representing the interaction of the calibration process with memory. Before triggering the calibration, it is important to reset the calibration circuit, so that all the retained values are flushed out. Calibration logic can then be triggered by sending a low value to the reset signal. The whole calibration process is controlled by a main controller FSM shown in Fig. 8 where the text in ovals represents state name/output1, output2. Output1 corresponds to the status of output flag CalComplete in Fig. 7 and marks completion of the calibration process when it is '1'. Output2 corresponds to the weight obtained after the calibration. Fig. 7Open in figure viewerPowerPoint Inputs and outputs of calibration logic and memory interface Fig. 8Open in figure viewerPowerPoint FSM of calibration controller During the calibration process of stage i, ADC output bits obtained from stage i to stage 14 are read from memory one by one. After stage i is calibrated, i is decremented and the corresponding state is calibrated next. This goes on until first pipelined stage is calibrated. Weight (w1) obtained after calibration of pipelined stage 1 is the final weight that is sought for. 5 Simulation results The calibration logic is implemented on Xilinx Basys-3 Artix-7 FPGA board in Verilog HDL as an FSM. The simulation output of the logic with input and output signals are shown in Fig. 9a. Flag 'CalComplete' and 32-bit wide signal 'FinalWeight' are the outputs of calibration logic, representing the completion of the calibration and final weight value, respectively. Fig. 9Open in figure viewerPowerPoint Simulation and Implementation(a) Simulation results, (b) Area occupied by the proposed algorithm in Artix-7 FPGA, (c) Hardware implementation in Basys3 FPGA board Entire calibration logic for 12-bit 100-MS/s pipelined ADC (with op-amp open-loop gain of 40 V/V) completes its task of determining the final weight in 1762 clock cycles or 35.3 µs with 100 MHz clock. ADC noise has not been considered in the analysis; it will increase the convergence time of the calibration if considered. The output signal 'FinalWeight' has 32-bit binary value '0011111100000111000 1011101011011' shown in Fig. 9c which is equal to in decimal equivalent of floating point binary representation. Thirty-two-bit width of 'FinalWeight' is limited by the internal hardware architecture of Basys-3 FPGA, whereas it requires a minimum of 23 bits when implemented in Synopsys Design Compiler. The resource utilisation report post-implementation for the Artix-7 FPGA is shown in Table 1. It covers only 5.9% of available LUTs and 16.7% of available DSP slices. Table 1. Utilisation report in Artix-7 FPGA Resource Utilisation Available Utilisation % LUT 1230 20800 5.91 LUTRAM 24 9600 0.25 FF 605 41600 1.45 DSP 15 90 16.67 IO 35 106 33.02 BUFG 1 32 3.13 Fig. 9b shows the leaf cells of different blocks of the proposed algorithm after implementation in Artix-7 FPGA with different colour coding to differentiate them. As shown, the proposed algorithm occupies <10% of total area available in the FPGA. Fig. 9c shows the weight display after the embedding the code in the Xilinx BASYS-3 Artix-7 FPGA kit. Post-implementation power consumed by the different blocks of the proposed algorithm in Artix-7 FPGA is shown in Fig. 10. The high value of static power shown in the figure includes the power of the whole FPGA including that of calibration part. Before calibration, DNL and INL is in the range of −1/0.63 LSB and −60/60 LSB, respectively, which improves to −0.63/+0.7 LSB and −0.77/+0.77 LSB, respectively, after calibration as shown in Fig. 11. Fig. 12 shows the fast Fourier transform response (4096 points) of the 12-bit 100 MHz pipelined ADC before and after the calibration. Signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) improve significantly from 35.92 and 36.73 to 75.36 and 82.29 dB, respectively, indicating the effectiveness of the proposed calibration algorithm. Fig. 10Open in figure viewerPowerPoint Post-implementation power consumption in Artix-7 FPGA Fig. 11Open in figure viewerPowerPoint DNL and INL of 12-bit pipelined ADC(a) Before, (b) After calibration Fig. 12Open in figure viewerPowerPoint SNDR and SFDR of 12-bit pipelined ADC(a) Before, (b) After calibration The foreground digital calibration technique for the pipelined ADC proposed in this work proves to improve the static and dynamic performance parameters and is time efficient also. Table 2 compares this work to different prior works done on calibration of 12-bit pipelined ADC. It can be noted that the foreground calibration method discussed in this work achieves more SNDR and effective number of bits (ENOB) when compared with other works with the same resolution. Table 2 also shows power-speed efficiency of the present work with earlier published work. This work does not require a reference ADC, thus saves the area and power required in designing a reference ADC. In comparison to [25], this work consumes more power because of lower sampling rate and slower calibration speed in the former. Area comparison could not be done as the proposed calibration algorithm was implemented in Xilinx Artix-7 FPGA which shows the results in terms of number of LUTs, DSP slices etc. (as shown in Table 1), not in terms of the number of gates as mentioned in other works where calibration was part of ASIC. Also, the internal architecture of LUT and DSP slice is not available to the user in order to find the gate equivalency. Table 2. Comparison of this work to prior works in pipelined ADC calibration Parameters [16] [23] [25] [26] This work resolution, bits 10 14 14 10 12 sampling rate, MS/s 500 51.2 20 100 100 calibration method foreground foreground foreground foreground foreground DNL (LSB) before calibration −1/1.5 — +0.35/–0.29 –1 –1/+0.61 after calibration 0.4 — +0.34/–0.28 –0.12 –0.63/+0.7 INL (LSB) before calibration 40 — +3.78/–4.59 10 –60.25/+60.30 after calibration 1 — +1.53/–2.71 ±0.3 –0.77/+0.77 SNDR, dB before calibration 28.28 65.42 68.6 32 35.92 after calibration 55.64 78.44 71.6 60 75.36 SFDR, dB before calibration — 70.68 74.8 34 36.73 after calibration — 97.14 82.3 67 82.29 ENOB, bits — 12.74 11.6 — 11.22 area (in terms of number of gates)a 20 K 100 K 7450 — — power, mWa 8 250 1.1 — 17 calibration time 300 µs (3 × 104 cycles @100 MHz) 3 µs (7 stage are calibrated) 28.2 ms ≈328 µs (8 × 212 cycles @100 MHz) 35.3 µsb aArea and power of only digital calibration part is quoted. bWithout considering the ADC noise. 6 Conclusion Since there is no requirement of ideal reference ADC, the proposed calibration technique does not suffer from the delay of slow reference ADC, thus saving area, power, and design efforts. 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