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maj-$n$ Logic Synthesis for Emerging Technology

2019; Institute of Electrical and Electronics Engineers; Volume: 39; Issue: 3 Linguagem: Inglês

10.1109/tcad.2019.2897704

1937-4151

Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André I. Reis, Renato P. Ribas,

Advancements in Semiconductor Devices and Circuit Design

In general, existing logic synthesis methods for majority logic are limited to 3-input gates (maj-3). However, since majority gates with larger fan-in have been proposed for different emerging nanotechnologies, it has become important to consider such gates in the synthesis process. This paper proposes a novel majority logic synthesis flow where the gates can have an arbitrary number of inputs. The proposed approach is based on the relationship between majority and threshold logic functions. The proposed methods obtain an average reduction of 10% on the number of nodes when compared to a previous work that uses both maj-3 and maj-5 gates. When compared to the previous maj-3 synthesis, the average reduction on number of nodes is 14%.