High‐voltage gain SEPIC‐based DC–DC converter without coupled inductor for PV systems
2019; Institution of Engineering and Technology; Volume: 12; Issue: 8 Linguagem: Inglês
10.1049/iet-pel.2018.5940
ISSN1755-4543
AutoresMojtaba Heydari, Hossein Khoramikia, Alireza Fatemi,
Tópico(s)Photovoltaic System Optimization Techniques
ResumoIET Power ElectronicsVolume 12, Issue 8 p. 2118-2127 Research ArticleFree Access High-voltage gain SEPIC-based DC–DC converter without coupled inductor for PV systems Mojtaba Heydari, Corresponding Author Mojtaba Heydari heydari@qut.ac.ir Faculty of Electrical and Computer Engineering, Qom University of Technology, Qom, IranSearch for more papers by this authorHossein Khoramikia, Hossein Khoramikia Faculty of Electrical and Computer Engineering, Qom University of Technology, Qom, Iran Current affiliation: Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, IranSearch for more papers by this authorAlireza Fatemi, Alireza Fatemi General Motors global Research and Development, Propulsion Systems Research Lab, Warren, MI, USASearch for more papers by this author Mojtaba Heydari, Corresponding Author Mojtaba Heydari heydari@qut.ac.ir Faculty of Electrical and Computer Engineering, Qom University of Technology, Qom, IranSearch for more papers by this authorHossein Khoramikia, Hossein Khoramikia Faculty of Electrical and Computer Engineering, Qom University of Technology, Qom, Iran Current affiliation: Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, IranSearch for more papers by this authorAlireza Fatemi, Alireza Fatemi General Motors global Research and Development, Propulsion Systems Research Lab, Warren, MI, USASearch for more papers by this author First published: 01 July 2019 https://doi.org/10.1049/iet-pel.2018.5940Citations: 7 AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract A new single-ended primary-inductor converter (SEPIC)-based DC–DC converter suitable for photovoltaic (PV) systems is introduced. The proposed converter has the advantage of continuous input current which reduces the input voltage ripple across the PV panels. Furthermore, it can provide a higher-voltage gain at smaller duty cycles when compared with counterpart SEPIC-based topologies which feature the absence of a coupled inductor. A smaller duty cycle for a given voltage gain translates to a lower-current ripple of the inductors, reduced conduction losses, and alleviated voltage stresses of the semiconductor switches. The proposed converter also benefits from a simpler structure and control scheme. The operational principles and the steady-state analysis are studied under both continuous conduction mode and discontinuous conduction mode. A comparative study between the proposed converter and seven counterpart topologies is also included. A laboratory prototype was built and tested. The experimental results are discussed in light of the theoretical analysis. 1 Introduction In recent years, PV power generating capacity has rapidly developed due to a number of factors, including subsidies provided by governments, continuing cost declines and diversifying the energy mix in some countries [1]. The low-output voltage of solar photovoltaic (PV) cells [1] necessitates the use of high-voltage gain DC–DC converters for connecting the solar panels to the power grid [2, 3]. These utility-interface DC–DC converters should also feature continuous input current with low-harmonic content in order to ensure stable and accurate operation at the maximum power point. Furthermore, the high cost of a PV system poses strict requirements on the efficiency of DC–DC converters [4]. To reduce the conduction losses of this converter, low-voltage devices with lower ON resistance are preferred. Among conventional step-up DC–DC converters, the boost and single-ended primary-inductor converters (SEPICs) feature continuous input current. Also, these converters can theoretically reach high step-up voltage gain at extremely high duty cycles of the power switches. The parasitic elements in the converter circuits, however, limit the attainable voltage gain. Furthermore, operating at extreme duty cycles increases the voltage rating requirements of devices, and hence results in higher conduction losses. The narrow pulse current with high amplitude that flows through the output diode at extreme duty cycles also intensifies the diode reverse recovery and can exacerbate electromagnetic interference (EMI) [5]. Therefore, DC–DC converters with high-voltage gains and lower duty cycles of power switch have been the subject of research in recent years [6-29]. A primary solution for improving voltage gain and efficiency simultaneously is the use of isolated DC–DC converters. These isolated converters offer the turn ratio of the high-frequency (HF) transformer as an additional design parameter to increase the voltage gain while keeping the duty cycle within an optimal range for higher efficiency [6-8]. However, in these isolated converters, the circuit operation is sensitive to the leakage inductance of the HF transformer, which needs to be tightly designed, in order to prevent the occurrence of momentary overvoltage across switches and power diodes. In addition, isolated DC–DC converters are larger in size than other converters and system efficiency could be affected due to an intermediary DC/AC/DC power conversion step. Furthermore, common ground between the input source and output in these converters is not provided which could limit their implementation for transformer-less grid-connected PV applications [9]. Non-isolated high step-up DC–DC converters which employ several innovative techniques such as switched capacitors/switched inductors structures [10-13], cascaded converters [14, 15], voltage-lift [16, 17], multilevel converters [18], coupled-inductor technique [5, 19-22], and voltage multiplier cells [23-25] are amongst the exemplary work in the literature to provide an alternative solution to isolated DC–DC converters. Several of these non-isolated high step-up DC–DC converters are derived from the conventional SEPIC converter [4, 12, 13, 16, 17, 20-22, 24-28]. The high step-up SEPIC-based converters have received particular attention in PV systems due to several advantages such as continuous input current, non-inverting output voltage polarity, low amount of EMI owing to low-input current ripple, and common ground between the input source and the output and output short-circuit protection [22]. The combination of a switched capacitor and switched inductor with classical SEPIC converter is discussed in [12, 13]. In these structures, the voltage gain is improved at the cost of higher voltage and current stress of the switch. Similarly, use of the voltage-lift technique presented in [16, 17] suffers from high-current stress of the main switch which degrades the efficiency. In [4], a new SEPIC-based converter with low-voltage stress on the main switch is proposed. However, the voltage gain is still low in this converter. A different approach to obtain high step-up voltage gain utilising coupled inductors has been proposed in [20-22, 24-29]. However, due to the leakage inductance of the coupled inductors, instantaneous overvoltages across the switches occur at switch turn-off, which increases the losses and reduces the system efficiency and reliability. In addition, to achieve a higher-voltage gain in these converters, it is necessary to increase the turns ratio of the coupled inductor, which increases the leakage inductance and exacerbates the above-mentioned issues. Several active and passive Snubber circuits have been proposed to recuperate leakage energy as well as to reduce the switches overvoltage [28, 29]. Although these circuits help, some major challenges associated with the use of coupled inductors remain unsolved. First, if the coupled inductor is placed at the input of the SEPIC converter, its leak inductance leads to a high ripple of the input current or even discontinuous current, which compromises the advantage of the continuous input current of the SEPIC converter and incurs extra losses. In addition, the use of coupled inductors increases the size and price of the converter. To simultaneously achieve high-voltage gain and high efficiency, a new SEPIC-based DC–DC converter is proposed in this paper which does not use a coupled inductor in its structure. The proposed converter has the advantage of a SEPIC converter in terms of continuous input current. The gain of the proposed converter is higher than the conventional SEPIC converter and other high step-up SEPIC-based converters without coupled inductors. Compared to the counterpart converter in [4], the proposed converter provides higher step-up voltage gain and higher efficiency, thanks to the reduced duty cycle of the power switch. However, the components count of the converter in [4] is smaller than the proposed converter which results in smaller volume and higher-power density of the counterpart converter. It is noteworthy that obtaining high-voltage gain with high efficiency and high-power density at the same time are conflicting objectives and an optimal compromise should be made to meet the specific application requirements of the target application. The characteristics of the proposed converter are as follows: High-voltage gain at low duty cycles of the power switch. Low-voltage stress on semiconductors which reduces conduction loss and increases the efficiency. Continuous input current and common ground between the input source and output. Low-input current ripple and split of the input DC bias current between two inductors which reduce the size of the inductors. This paper is organised as follows: the operational principles and steady-state analysis of the proposed converter in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) modes are discussed in the next section. In Section 3, the voltage gain and the efficiency of the converter are calculated considering the power loss in switches, diodes, and inductors. Design considerations for the proposed converter modules are presented in Section 4. A thorough comparison between the proposed converter's performance and recently introduced counterpart converters are discussed in Section 5. The theoretical analysis and the proper performance of the proposed converter are validated by experimental results in Section 6. 2 Configuration and operating modes of the proposed converter The structure of the proposed converter is shown in Fig. 1. According to Fig. 1, the proposed converter consists of four capacitors, three inductors, two power switches, and three diodes. For circuit analysis, it is first assumed that the converter operates in CCM. In addition, all circuit components are assumed to be ideal and lossless, and all the capacitors are assumed to be large enough, and thus their voltage is constant at steady state. In addition, it is assumed that the small current ripple of inductors has negligible effects on calculating the converter gain. Fig. 1Open in figure viewerPowerPoint Structure of the proposed converter The waveforms of the proposed converter in the CCM mode are shown in Fig. 2a. On the basis of Fig. 2a, for each switching period Ts, there are two operating modes with time intervals of d1Ts and d2Ts, where d1 and d2 are the duty cycles of each operating mode. In addition, in steady state, since the average voltage of L1, L2, and L3 is zero, the following equations can be provided based on the structure of the proposed circuit: (1) Fig. 2Open in figure viewerPowerPoint Waveforms of the proposed converter (a) CCM mode, (b) DCM1 mode 2.1 First mode [t0, t1] In this case, S1 and S2 switches are on and the D1–D3 diodes are reverse biased. The waveforms of the currents and the current path of the proposed converter are shown in Figs. 2a and 3a, respectively. In this mode, charging is as follows: L1 through Vin, L2 through Vin and C1, and L3 through C1–C3. The energy stored in C4 is discharged in the output load. Fig. 3Open in figure viewerPowerPoint Current path of the proposed converter in CCM (a) First mode, (b) Second mode On the basis of Fig. 3a and (1), the inductors voltage can be expressed as follows: (2) (3) (4) 2.2 Second mode [t1, t2] In this case, S1 and S2 are off and D1–D3 diodes are turned on. The waveforms and current paths in the second mode are shown in Figs. 2a and 3b, respectively. In this mode, charging is as follows: C1 through Vin and L1, C2 through Vin and L2, C3 through L3, and C4 through Vin and L2–L3. According to Fig. 3b and (1), the inductors’ voltage in the second state can be expressed as follows: (5) (6) (7)Using the voltage-seconds rule on inductor Li (i = 1, …, 3), the following equation can be deduced: (8)Considering (2)–(4) and (5)–(7) and using (8), one can find that (9) (10) (11)After simplifying (9)–(11) and considering D = d1 and d1 + d2 = 1, the voltage of the capacitor would be as follows: (12) (13) (14) (15)The final gain of the proposed converter in the CCM mode can be calculated as follows: (16)Fig. 2b shows the operation of the proposed converter in DCM1 mode. In this mode at [t3, t5], the current of L1 is equal to the current of D1; in addition, at [t4, t5] the total current of L2 and L3, which is equal to the current of D3, is zero. Therefore, the diodes are turned off before the switches are turned on, resulting in a new duty cycle. There are two other DCM modes available in the proposed converter. In one of these modes, i.e. DCM2, in each switching cycle, the L1 current is zero, resulting in D1 to be turned off before S1 is turned on, while D3 remains on until S2 is turned on. In the other mode, i.e. DCM3 mode, the total current of L2 and L3 is zero, thus turning D3 off before S2 is turned on, while D1 remains on until the switch S1 is turned on again. The theoretical analysis of different DCM modes, i.e. DCM1, DCM2, and DCM3, are not discussed here for brevity. However, the circuit gains are provided as follows. Considering D = d1, the gain in DCM1 is given in the equation below: (17)where In DCM2, the voltage gain of the circuit can be calculated as follows: (18)In DCM3, the voltage gain is as follows: (19)To obtain the values of inductors in CCM, the capacitor currents are expressed as follows: (20) (21) (22) (23)Using the principle of current-seconds of capacitors we have the following equations: (24) (25) (26) (27)Using the integral form of the equation of the inductor current, the current ripple can be obtained (28) (29) (30)To operate in CCM mode, the equations IL1>ΔiL1 and IL2 + IL3>ΔiL2 + ΔiL3 must be established, which can be expressed as follows: (31) (32)Then we have If both (31) and (32) are not satisfied, the converter operates in DCM1 mode. If only condition (32) is satisfied, the converter works in the DCM2 mode, and if only condition (31) is satisfied, then it operates in the DCM3 mode. Fig. 4 shows the different operating modes of the proposed converter for the hypothetical values of K and K'. Fig. 4Open in figure viewerPowerPoint Different operating modes of the proposed converter for hypothetical values of K and K' Therefore, the minimum inductor values can be calculated for CCM mode as follows: (33) (34)In addition, based on (12)–(15), the voltage stresses of the power switches and diodes can be calculated as follows: (35) (36) (37) (38) (39)Also, the current stresses of the switches are as follows: (40) (41) 3 Analyses of losses of the proposed converter Most of the power losses in the proposed converter could be attributed to the power losses in switches, diodes, and inductors. For simplification, the equivalent series resistance (ESR) of capacitors is neglected. Taking into account the conduction losses of semiconductors and inductors, the equivalent circuit of the proposed converter is shown in Fig. 5. The loss analysis of the proposed converter is done using the small ripple approximation method. Accordingly, the capacitors and inductors are assumed to be large enough and the voltage of the capacitors and the current of the inductors are almost constant. Fig. 5Open in figure viewerPowerPoint Equivalent circuit of the proposed converter considering the conduction losses Using the voltage-seconds balance principle for inductors and the ampere-seconds balance principle for capacitors, the voltage gain of the proposed converter, in this case, can be calculated using (42) The efficiency of the proposed converter can be calculated through (42) and by considering Iin = IL1 + IL2 (42) (43)Given (42) and (43), it can be concluded that if the input voltage is much larger compared with the sum of the diodes’ conduction voltage, and the load resistance (R) is much larger than the sum of the resistances of semiconductors and inductors, then the efficiency of the proposed system would be greater. Fig. 6 compares the efficiency of the proposed converter and the SEPIC converter at different voltage gains. The gain and efficiency of the proposed converter are calculated through (42) and (43) and one can calculate the gain and efficiency of the SEPIC converter in the same manner. Although, with the same voltage gain, the voltage stress of the proposed converter switches is less than that of the SEPIC converter, and therefore the RON resistance is lower in the proposed converter, yet for simplicity, the RON resistance of the switches in both converters is considered to be equal in Fig. 6. It could be seen that at a high-voltage gain, the proposed converter presents higher efficiency than the SEPIC converter. It is not possible to achieve gains over 4.5 in the SEPIC converter due to the higher duty cycle of switches, resulting in very high conductivity losses, while it is possible to achieve a higher gain in the proposed converter. Fig. 6Open in figure viewerPowerPoint Comparison of the efficiency between the proposed converter and the SEPIC converter at different voltage gains In (43), the switching losses are neglected. The switching losses of the S1 and S2 switches, which are equal to the sum of the ON and OFF switching losses, are as follows, assuming that the output capacitors of the metal–oxide–semiconductor field-effect transistors (MOSFETs) are linear [30]: (44) (45)where Co1 and Co2 are, respectively, the output capacitors of the S1, S2 MOSFETs, and VDS1 and VDS2 are their drain–source voltages. Considering (44) and (45) and comparing them with the switching losses in the SEPIC converter, it could be observed that the switching losses of the proposed converter are less than the SEPIC converter since, for a given voltage gain M, the SEPIC converter requires a larger duty cycle, and the drain–source voltage of MOSFET in the SEPIC converter is much higher than the sum of the drain–source voltages of the two MOSFETs of the proposed converter. 4 Design considerations for the proposed converter In this section, the main design equations of the proposed converter in CCM mode are presented through an example with the following specifications: Output power: 150 W. Input voltage: 20 V. Output voltage: 80 V. Switching frequency: 20 kHz. Considering the voltage gain equation in (16), the value of the duty cycle is calculated to be 0.37. 4.1 Calculating the voltage of switches and power diodes The voltages of S1 and D1 are equal to the voltage of C1, which according to (35), it is 31.59 V. Also, the voltage of S2 is equal to the voltage of C2, which according to (36), it is 49.9 V. It is clear that the reverse block voltage of the switches in the proposed converter is always lower than the output voltage of the converter, which is one of the advantages of this converter. The voltage of D1, according to (37), is equal to the voltage across C1 (31.59 V). However, since the circuit is not ideal and due to a reverse diode current as well as parasitic capacitors and inductors, the voltage of D1 can increase to 40 V. The values of the voltages of D2 and D3, according to (38) and (39), are equal to 81.49 V, which, due to the same reason as mentioned above, in practise, their voltage will be slightly higher than these values and this will be considered in the selection of circuit elements. 4.2 Calculation of L1–L3 If the inductor current ripple is assumed to be about 30% of its average current, according to (25)–(27), the average inductor currents are 3.43, 4.87, and 1.87 A, respectively, for L1–L3. Accordingly, the value of the inductors could be calculated based on (28)–(30) 4.3 Calculation of C1–C4 Using the integral form of the voltage equation of capacitors, as well as (20)–(23) and (24)–(27), their capacitances can be calculated using the following equations: To obtain the value of the capacitors, their total voltage ripple (2ΔvC) is considered to be 10% of their average voltage. Therefore, given the above equations, the capacitances of C1–C4 are determined to be 35, 7, 13, and 4.8 μF, respectively. 5 Comparison between different converters In Table 1, a comparison is made between the number ofcomponents, the voltage gains, and the voltage stresses on the semiconductors of theproposed converter, the conventional SEPIC converter, cascaded SEPIC converters(SEPIC2), SEPIC converter cascaded with modified SEPIC converter(MSEPIC2) and other counterpart step-up converters recentlyintroduced in the literature. Table 1. Comparison between the proposed converter and other converters Reference Converter components Gain Switch voltagestress Diode voltage stress Switch Diode Capacitor inductor proposed converter 2 3 4 3 , conventional SEPIC 1 1 2 2 SEPIC2 2 2 4 4 , , MSEPIC2 2 3 5 4 , , converter [31] 1 4 2 3 , converter [32] 2 1 1 2 converter [33] 2 7 1 4 converter [34] 1 3 2 2 , , Since the proposed converter does not use a coupled inductor to increase the voltagegain, this paper compares the proposed converter with other step-up converters whichdo not use coupled inductors. For a better illustration, the voltage gain andvoltage stress of semiconductors in different converters are compared in Figs. 7–9. Fig. 7Open in figure viewerPowerPoint Comparison of the voltage gain between differentconverters Fig. 8Open in figure viewerPowerPoint Comparsion of the voltage stress of switches between thedifferent converters Fig. 9Open in figure viewerPowerPoint Comparsion of the diodes inverse voltage between differentconverters According to Fig. 7, for a given duty cycle, the voltage gain of the proposed converter is higher than that of other converters, which reduces the current ripple of the inductors, conduction losses, and voltage stress of the semiconductor switches. The voltage stresses of the switches versus the voltage gain are compared between the proposed converter and other converters in Fig. 8. As can be seen in this figure, for the same voltage gain, the sum of the voltage stress on the switches in the proposed converter is lower than that of the other converters, allowing the use of lower-voltage MOSFETs with lower RONs, which decreases the conduction loss in the proposed converter. A comparison of the diodes’ voltage stress between different converters is presented in Fig. 9. Accordingly, with one exception, the sum of the voltage stress across the diodes in the proposed converter is less than or almost equal to that of the other converters. This enables the selection of components with smaller sizes for the proposed converter compared with other converters for a given power. As a result, the proposed converter best suits the applications which require higher power and voltage gains, thanks to lower-voltage ratings of components, reduced conduction losses, and improved efficiency. 6 Experimental results To verify the performance of the proposed converter, a prototype with the followingspecifications was built and tested: input voltage of 20 V, the output voltage of80 V and maximum output power of 150 W. The prototype of the proposed converter isshown in Fig. 10 and the system parameters areprovided in Table 2. The control circuitconsists of a pulse-width modulation (SG3524) controller and two TLP250optocouplers, the structure of which is shown in Fig. 11. In the following section, the proposed converter is tested underboth CCM and DCM conditions. Table 2. Experimental parameters Variable value input voltage 20 V output voltage 80 V L1,L2,L3 300, 320,720 μH C1 47 μf C2,C4 10 μf C3 22 μf switching frequency 20 kHz D1–D3 MBR20150PT (150 V/15 ns) 30CPQ100 (100 V/10 ns) S1–S2 IRFZ44N (55 V,RDS(ON) = 17.5 mΩ) IRF540N (100 V,RDS(ON) = 44 mΩ) load power 150 W Fig. 10Open in figure viewerPowerPoint Prototype of the proposed converter Fig. 11Open in figure viewerPowerPoint Power switches control circuit diagram Fig. 12 shows the steady-state waveforms of the proposed converter in CCM mode. Fig. 12a shows the currents of L1 and L2 and Figs. 12b and c, respectively, display the voltage and current waveforms of S1 and S2. Given (35) and (36), the voltage stresses of the switches are ∼32 and 50 V, respectively. Figs. 12d and e represent the current waveforms of D1–D3. Fig. 12e also shows the current of L3 which confirms the performance of the proposed converter in CCM mode. Fig. 12Open in figure viewerPowerPoint Experimental waveforms of the proposed converter in CCM mode Fig. 12f represents the voltage of C1 and the voltage of C2, which according to (12) and (13) are 32 and 52 V, respectively. The voltage of C4 is equal to the output voltage of the converter, which is 80 V. Considering four times voltage gain of the proposed converter prototype, the duty cycle of the power switches is in good agreement with a duty cycle of 0.38 obtained from (16). The small difference between the output voltage and the voltage obtained from (16) is due to the losses found in the prototype elements, which were neglected in the calculation of (16). To validate the DCM operation of the proposed converter, the steady-state waveforms in DCM3 mode are provided in Fig. 13. To operate in the DCM mode, the load resistance is raised to 224 Ω and the duty cycle is reduced to 0.29. The other parameters are similar in value to the CCM mode parameters. As can be seen in Figs. 13a–c, the total current of L2 and L3 declines to zero during the switch-OFF state, thus turning D2 and D3 off before the switches are turned on (as shown in Figs. 13b and c), while D1 remains on until the switches are turned on again (as shown in Fig. 13b). Fig. 13d depicts the voltages of C1 and C2 and the output voltage of the proposed converter in this mode. The output voltage is consistent with the theoretical value expressed in (19). Fig. 13Open in figure viewerPowerPoint Experimental waveforms of the proposed converter in DCM3 mode Comparison of the theoretical, simulated, and experimental voltage gain (M = Vo/Vin) is depicted in Fig. 14. As is reflected in this figure, the theoretical voltage gain is consistent with the measured waveform up to D = 0.6. No attempt was made to increase the duty ratio more than 0.6 since the voltage across the switches of the prototype will exceed the rated values. In addition, the measured efficiency of the prototype is shown in Fig. 15 for a wide range of output power. According to this figure, the proposed converter demonstrates a higher performance at the high-voltage gain and different load conditions. In all the ranges, the converter operated in CCM mode. Fig. 14Open in figure viewerPowerPoint Theoretical, simulated and experimental voltage gain versus duty ratio D Fig. 15Open in figure viewerPowerPoint Measured efficiency of the proposed converter 7 Conclusion This paper proposed a new coupled-inductor-less SEPIC-based DC–DC converter with high-voltage gain, which could achieve higher-voltage gains at lower switching duty cycles. This resulted in a lower-current ripple, lower-voltage stresses of the switches and diodes, and lower-power losses of the semiconductors, thus increasing the efficiency and reliability of the converter. The CCM and DCM operating modes of the proposed converter were thoroughly studied through the analytical equations. A 150 W prototype was built and experimental results were presented to verify the performance of the proposed converter. The experimental results indicated that the proposed converter was able to operate at high-voltage gains with low duty cycles of power switches, which reduce the current ripple of inductors, conduction losses, voltage stress of semiconductor switches, and thus makes the proposed converter a suitable candidate for PV systems or other renewable energy applications. 8 References 1Chen W.-L., and Lin J.-S.: ‘One-dimensional optimization for proportional–resonant controller design against the change in source impedance and solar irradiation in PV systems’, IEEE Trans. Ind. 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