Ultra‐high step‐up two‐input DC–DC converter with lower switching losses
2019; Institution of Engineering and Technology; Volume: 12; Issue: 9 Linguagem: Inglês
10.1049/iet-pel.2018.5924
ISSN1755-4543
AutoresParham Mohseni, Seyed Hossein Hosseini, Mohammad Maalandish, Mehran Sabahi,
Tópico(s)Multilevel Inverters and Converters
ResumoIET Power ElectronicsVolume 12, Issue 9 p. 2201-2213 Research ArticleFree Access Ultra-high step-up two-input DC–DC converter with lower switching losses Parham Mohseni, Parham Mohseni Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorSeyed Hossein Hosseini, Corresponding Author Seyed Hossein Hosseini hosseini116j@yahoo.com orcid.org/0000-0002-3716-0126 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran Engineering Faculty, Near East University, Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorMohammad Maalandish, Mohammad Maalandish Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorMehran Sabahi, Mehran Sabahi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this author Parham Mohseni, Parham Mohseni Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorSeyed Hossein Hosseini, Corresponding Author Seyed Hossein Hosseini hosseini116j@yahoo.com orcid.org/0000-0002-3716-0126 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran Engineering Faculty, Near East University, Nicosia, North Cyprus, Mersin 10, TurkeySearch for more papers by this authorMohammad Maalandish, Mohammad Maalandish Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this authorMehran Sabahi, Mehran Sabahi Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, IranSearch for more papers by this author First published: 10 July 2019 https://doi.org/10.1049/iet-pel.2018.5924Citations: 19AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract In this study, a novel isolated ultra-high step-up two-input DC–DC converter with low-voltage stress across semiconductors is presented. In the proposed converter, outputs are isolated from the inputs by a high-frequency transformer and the leakage inductance of the transformer is used to soft switching (zero-current switching) of the power switches when they are turned-on and alleviate the reverse recovery problems of the diodes. This converter can be operated as an interleaved single-input converter with a 180° phase shift. The converter benefits from the advantages of both the conventional boost converter and diode-capacitor voltage multiplier (VM) stages. The primary side of the transformer consists of two-input cells based on the conventional boost converter and the secondary side consists of diode-capacitor VM stages which are used to increase the voltage gain and decrease the nominal voltage stress across semiconductors. To confirm the converter performance, the mathematical analysis and simulation result are presented, in addition, the comparison between the proposed converter and other converters which are presented in recent studies is presented. An experimental prototype 410 V/280 W of the converter with 40 and 45 V input voltages is provided to illustrate the correct operation of the presented converter. 1 Introduction Nowadays, because of the lack of fossil fuels and their atmosphere pollution problems, renewable energy sources such as photovoltaic (PV) panels, wind turbines (WTs) and fuel cell (FC) systems are widely being used to generate electricity [1, 2]. The generated voltage of PV panels is low. To increase the output voltage level of the PV panel, using DC–DC power converters is one of the suitable methods. Besides the increasing voltage, the low-input current ripple is essential for these kinds of converters, because low-current ripple increases the lifetime of PV panels and FC systems [3]. To enhance the input voltage value, conventional buck–boost and boost converters need large duty cycles for power switches due to their limited voltage gains. Large duty cycles increase the current stress on power switches, increase the output voltage and input current ripple that reduces the conversion efficiency and increase the reverse recovery problems of diodes [4]. In [5], an interleaved non-isolated transformerless DC–DC converter with high-voltage gain is presented. In that structure, the active switched inductor and passive switched-capacitor are used to increase the input voltage. In [6, 7], two topologies of non-isolated high step-up DC–DC converters are presented. In these topologies, both the coupled inductors and voltage multipliers (VMs) methods are combined to provide high-output voltage without a large duty cycle. Three structures of high step-up interleaved DC–DC converters are presented in [1, 8, 9]. In these structures, the leakage inductances of coupled inductors or high-frequency (HF) transformers are utilised to zero-current switching (ZCS) turn ON for power switches and alleviate the reverse recovery problems of diodes. In [10-12], three high-voltage gain step-up interleaved DC–DC converters with zero-voltage switching (ZVS) operation are presented. The converter presented in [12] is a buck–boost bidirectional converter, in which the ZVS turn ON is provided for the active switches in both bucks and boost operations. Zero-current transition methods for diodes and zero-voltage transition methods for power switches can be provided for HF interleaved DC–DC converters [13-15]. In isolated converters, HF transformer is used for galvanic isolation which satisfies the requirements for safety regulations and increases the voltage gain of the converter for high-voltage applications [16]. In [17], an interleaved isolated high step-up DC–DC converter with the semi-active more quadruple rectifier for the secondary-side rectification service. In this converter, the power losses are improved by using semiconductors with low-voltage rate, ZVS turn ON for power switches and ZCS turn OFF for diodes. Owing to the dependence of the renewable energy sources such as PVs and WTs to environmental conditions, it needs to hybrid the alternative input sources for grid-connected or stand-alone systems. A multi-input DC–DC converter can be a suitable converter with compact structure and low cost to combine different input sources with various voltage-power characteristics. In [18-21], some non-isolated multi-input high step-up DC–DC converters are proposed for PV applications. In the presented converters, the output voltage level increases by increasing the number of inputs. However, in [18], there are some limitations for increasing the number of input stages because of the high-voltage stress on the power switch of the last stage and the output diode. In [22], an isolated multi-input boost DC–DC converter has proposed for different renewable energy resources. This converter is applied for simultaneous power management of different PV panels, different WT generators, wind/solar and wind/solar/battery hybrid generation systems. To increase a low-input voltage to a high-output voltage, some kinds of diode-capacitor VM techniques have been presented in previous works [22]. One kind of these VM techniques (conventional Dickson charge pump VM technique) for AC isolated/non-isolated and DC input voltages are shown in Figs. 1a and b, respectively. These techniques [Cockcroft–Walton (CW) [23], conventional and modified Dickson charge pump [4, 24] and bi-fold Dickson [25, 26] VM techniques) have been utilised in some current fed high step-up DC–DC converters as single-input interleaved and dual input. The output voltage level of these converters depends on the number of VM stages. There is a restriction with the converters based on CW VMs that the output impedance increases rapidly by increasing the number of VM stages. Therefore, for the high-voltage gains, the efficiency of these kinds of converters would be reduced. The VMs based on bi-fold Dickson just work for even number of diode-capacitor VM stages, and the VMs based on modified Dickson just work for the odd number of diode-capacitor VM stages. In Fig. 1c, an interleaved high step-up DC–DC converter based on conventional Dickson charge pump diode-capacitor VM stages is presented. To add an additional freedom degree to increase the converter output voltage level, isolate the output side from input side, decrease the normalised voltage stresses across the power switches, decrease the switching losses of the power switches and reverse recovery problems of the diodes, and as a result improves the converter efficiency the combination of an HF transformer with two-input inductors can be used as it is shown in Fig. 1d. To promote the converter operation as a dual-input converter with the different input voltage and current characteristics, just an energy storage capacitor should be placed in series with the transformer to store the voltage difference between the two-input sources and prevent the negative current in the input cell with lower-voltage value. Therefore, by adding an input power supply, a dual-input single-output converter is provided, also able to produce a high-voltage gain and lower-voltage stress on the power switches. In addition, by providing an extra freedom degree in design, the turn ratio of the transformer and the number of VM stages can be provided two independent design values to select proper low-rated switches and diodes, respectively. Also, the leakage inductance of the transformer is utilised to improve the converter efficiency with reducing switching losses of the switches and reverse recovery problems of the diodes. Fig. 1Open in figure viewerPowerPoint Synthesis of the dual-input high step-up DC–DC converter (a) AC rectification circuit, (b)Voltage fed circuit with VM stages, (c)Non-isolated interleaved high step-up converter based on VM stages,(d) Isolated interleaved highstep-up converter based on VM stages In this paper, a new ultra-high step-up isolated two-input DC–DC converter structure is proposed with the following features: Simply controllable input sources with the simultaneous operation and continuously input currents are provided to supply common load. Also, the converter can continue its operation while each of the input sources has a fault or it is not able to provide the load power. The output is isolated from the inputs using an HF transformer, and the leakage inductance of the transformer is used to ZCS turn ON for the power switches and alleviates the reverse recovery problems of the diodes. The output voltage level depends on the number of VM stages and the turn ratio of the transformer that there is no limitation to increase the VM stages. The voltage gain increases and the normalised semiconductor voltage stress decreases by increasing the number of VM stages and the turn ratio. Therefore, utilising the low-rate semiconductors increases the conversion efficiency. The proposed converter can operate as a single-input converter in the interleaved manner which reduces the input current ripple. Therefore, these features make the proposed converter as a suitable converter to utilise in renewable energy applications with high efficiency. 2 Presented converter structure and operation modes The circuit of the isolated step-up two-input single-output DC–DC converter with some number ofdiode-capacitor VM stages is illustrated in Figs. 2a and b. In these figures, S1 andS2 are the power switches of the input cells,L1 and L2 are the filterinductors of the input cells, Lk is the total primaryand secondary transformer leakage inductances that reflected the primary side; andLm is the magnetising inductance of the transformer.Np are the turns of the primary winding andNs are the turns of the secondary winding of thetransformer. The capacitor Cs is used to store thevoltage differences between the input sources. The secondary side of the transformeris composed of diode-capacitor VM stages that the voltage gain and normalisedvoltage stresses on the semiconductors depend on the number of them. Fori = {1, 2, 3, …}, Ci andDi are the capacitor and diode of theith VM stage, respectively. Coutand Dout are the output capacitor and a diode,respectively. Fig. 2Open in figure viewerPowerPoint Topology of the presented isolated multi-input–single-outputDC–DC converter (a) With even number of VM stages,(b) With odd number of VM stages,(c) With three number of VMstages, (d) Key waveforms First operation mode [t0, t1]: According to Fig. 3a, in this mode, both the powerswitches S1 and S2 are in ONstate. Both the inductors L1 andL2 are magnetising through the input voltagesVin1 and Vin2,respectively, and their currents are increasing linearly. The VM diodes are reversebiased and the VM capacitors are not charged or discharged and their voltage remainsconstant. Therefore, the primary and secondary currents of the transformer are zeroand the currents of the leakage and magnetising inductances are equal. When both thepower switches are in ON state, the total voltage across the leakage and magnetisinginductances are equal to the reverse voltage of capacitorCs. the output load is fed by the output capacitorCout. So for this operation mode, it can be writtenas (1) (2) (3) (4) Fig. 3Open in figure viewerPowerPoint The operation modes of the presented converter in CCMoperation (a) 1st mode[t0, t1],(b) 2nd mode[t1, t2],(c) 3rd mode[t2, t3],(d) 4th mode[t3,t4] Second operation mode [t1, t2]: The equivalent circuit of this operation mode is shown in Fig. 3b. At the moment of t1, switch S2 turns OFF and the parallel parasitic capacitor (Cs2) of S2 is charging by the total currents of inductor L2 and leakage inductance Lk. The current of leakage inductance Lk is changing direction from positive to negative. The voltage of S2 is increasing linearly and it can be written as follows: (5)Third operation mode [t2, t3]: In this mode (as shown in Fig. 3c), switch S1 is ON and switch S2 is OFF. The current of inductor L1 is increasing linearly. Diodes D1 and D3 are reverse biased and diode D2 and the output diode Dout are forward biased. The current in inductor L2 causes to create a negative current in the secondary winding of the transformer and charging the VM capacitor C2 and the output capacitor Cout, and discharging the VM capacitors C1 and C3. In this mode, the current of magnetising inductance Lm decreases to zero, and after a while it turns to negative. So it can be written as (6) (7) (8) (9) (10) (11) Fourth operation mode [t3, t4]: In this mode (as shown in Fig. 3d), at the moment of t3, switch S2 turns ON. Owing to the current in leakage inductance iLk, switch S2 turns ON in soft switching condition (ZCS). Fifth operation mode [t4, t5]: This operation mode whichis shown in Fig. 4a, issimilar to the first operation mode, with the difference that both the leakage andmagnetising inductances currents are negative (12) (13) (14) (15) Fig. 4Open in figure viewerPowerPoint The operation modes of the presented converter in CCMoperation (a) 5th mode [t4,t5],(b) 6thmode [t5, t6](c) 7th mode[t6, t7],(d) 8th mode[t7, t8] Sixth operation mode [t5, t6]: The equivalent circuit of this operation mode is shown in Fig. 4b. At the moment of t5, switch S1 turns OFF and the parallel parasitic capacitor (Cs1) of S1 is charging by the total currents of inductor L1 and leakage inductance Lk. The current of leakage inductance Lk is changing direction from positive to negative. The voltage of S1 is increasing linearly and it can be written as (16)Seventh operation mode [t6, t7]: In this mode (as shown in Fig. 4c), switch S1 is OFF and switch S2 is ON. The current of inductor L2 is increasing linearly. Diodes D2 and Dout are reverse biased and diodes D1 and D3 are forward biased. The current in inductor L1 causes to create a positive current in the secondary winding of the transformer and charging the VM capacitors C1 and C3, and discharging the VM capacitor C2 and the output capacitor Cout. In this mode, the current of magnetising inductance Lm decreases to zero, and after a while it turns to positive. So it can be written as (17) (18) (19) (20) (21) (22)Eighth operation mode [t7, t8]: In this mode (as shown in Fig. 4d), at the moment of t7, switch S1 turns on. Owing to the current in leakage inductance iLk, the switch S1 turns on with soft switching condition (ZCS). After this mode, the proposed converter returns to the first operation mode, the operation cycle is repeated. The presented converter, unlike the other topologies, does not work in discontinuous conduction mode at low-output powers. In other words, the presented converter operation modes change at low-output powers to prevent the converter operation in DCM mode. Unlike the other topologies, at third and seventh operation modes, the current values of the input inductors iL2(t) and iL1(t) are decreasing to the current value of the magnetising inductance iLm(t) instead of decreasing to zero at low-output powers. Or it can be said, at third and seventh operation modes, the currents through the primary and secondary windings of the transformer reach to zero, before both the power switches S1 and S2 turn to ON state at low-output powers. Therefore, the negative voltage values [(8) and (19)] across the input inductors L1 and L2 will be changed to positive values as (23) (24)Hence, the current values of the input inductors L1 and L2 start to increase at seventh and third operation modes, respectively. So, this converter performance at low-output powers prevents the converter to operate in DCM mode. As mentioned before, the presented converter can continue its operation and supply the output load while one of the input power resources has encountered a failure. This condition occurs when PV modules are completely shadowed or each of the input resources is not able to generate power in hybrid applications. When one of the input power supplies is disturbed, the other power supply can provide the output load power. To convert operation continuation in the open circuit or failure event of one of the power supplies, the corresponding body diode of the input cell power switch will be conducting while the power switch is in OFF state. 3 Calculation of output voltage To calculate the output voltage, the leakage inductance is ignored. Moreover also, the time intervals [t1, t2], [t3, t4], [t5, t6] and [t7, t8] are ignored due to their short time durations. By calculating the voltage-second balance law to the inductors L1 and L2, it can be written as (25) (26) In the above equations, M is the number of diode-capacitor VM stages, d1 and d2 are the duty cycles of power switches S1 and S2. By calculating the average voltage of the magnetising inductance Lm at a period of switching time, the voltage value of the capacitor Cs is obtained as (27)By using (25)–(27), the VM capacitors voltage and output voltage for M number of VM stages are obtained as follows: (28) (29) (30)Therefore, the output voltage of the presented converter with three number of VM stages is equal to (31)The obtained output voltage value in (31) is the ideal output voltage of the presented converter. Generally, the leakage inductance causes duty cycle losses, which reduces the converter output voltage. Therefore, the actual output voltage is lower than the value given in (31). The output voltage of the converter is calculated by applying the effect of the leakage inductance Lk as (32) The detailed analysis is presented in the Appendix. The presented converter can operate as a single-input interleaved converter, in which case there is no need for the storage capacitor Cs. In this case, the converter voltage gain for the same input voltage sources (Vin1 = Vin2 = Vin), the equal duty cycle for the power switches (d1 = d2 = d) and for the different values of M are equal as (33)To calculate the output voltage at low-output powers, the leakage inductance is ignored. Moreover also, the time intervals [t1, t2], [t3, t4], [t5, t6] and [t7, t8] are ignored. Using the voltage-second balance law to the inductors L1 and L2, the following equations are obtained as: (34) (35)where λ1 and λ2 are the time intervals that they start at t5 and t2, respectively, until the current of the secondary winding of the transformer reaches to zero [λ1<(1−d1)TS and λ2<(1−d2)TS]. By calculating the average voltage of the magnetising inductance Lm at a period of switching time, the voltage value of the capacitor Cs is derived as (27). Using (27), (34) and (35), the VM capacitors voltages and the output voltage of the converter for three number of VM stages are obtained as (36) (37)With regards to third and seventh operation modes in Figs. 3 and 4, it can be written for the leakage inductance current ripple as (38)So, the time intervals λ1 and λ2 are derived as (39). 4 Design of components 4.1 Magnetising elements When S1 is OFF and S2 is ON, the voltage across the primary side winding of the HF transformer is equal to (39) (40)where ΔB is the magnetic flux density variation and Ae is the magnetic core equivalent area. The turn numbers of the primary and secondary windings can be selected based on the appropriate transformer design guidelines. The apparent power of the HF transformer can be calculated by multiplying the root-mean-square (RMS) voltage and current of the primary winding. The current through the secondary side of the transformer is equal to the summation of the conduction currents of the diodes. Therefore, the primary winding RMS currents are obtained as (41) (42)The RMS value of the secondary winding current is equal to . According to (41) and (42), the diameters of the secondary and primary wires of the HF transformer can be calculated. Furthermore, the RMS voltage across the primary winding of the transformer is obtained as (43)The average current of the magnetising inductance Lm for different values of M is obtained as (44) (45)The magnetising inductance current for different modes of input voltages is shown in Fig. 5. The current ripple of the magnetising inductance can be obtained as (46)where ΔILm1 and ΔILm2 are shown in Fig. 4 and they can be calculated as (47) Fig. 5Open in figure viewerPowerPoint The current of magnetizing inductance for different modes of input voltages The values of the input inductors should be selected in such a way that the inductor currents iL1(t) and iL2(t) while their values are decreasing, does not reach to magnetising inductance current iLm(t) at seventh and third operation modes, respectively. Therefore, with regards to seventh and third operation modes, and Fig. 5 it can be written as the equation below: (48)Hence, in order to select the proper size for the inductors, the calculation of the current ripple and the average current for each of the inductors is required. The average current of the inductors L1 and L2 is calculated as (49) (50)The current ripples of the inductors L1 and L2 are obtained as (51) (52)Therefore, by placing (44)–(47) and (49)–(51) in (48), the minimum value of the inductors for various values of M can be calculated as (52) and (53). 4.2 Power switches design An important point to select the semiconductors is that they must withstand their voltage stress and conducting current. Therefore, it is necessary to calculate the voltage and current stresses on the power switches S1 and S2 to select the appropriate power switches to achieve optimal efficiency. The maximum blocking voltage of the power switches S1 and S2 is minimum and it can be expressed as (53) (54)The nominal voltage stresses on the power switches for the same input voltage sources, equal duty cycles, and different values of M are equal as (55)Therefore, the voltage stress across the power switches is easily reduced by increasing the number of VM stages M and turn ratio n of the transformer. The average current of each power switch is equal to its corresponding input current. So the current of each of the power switches S1 and S2 depends on its corresponding input power. 4.3 Power diodes design To select appropriate diodes, it is necessary to calculate the voltage and current stresses on the power diodes. The voltage stress on all the power diodes is equal and can be calculated as (56)The nominal voltage stress on the power diodes for equal input voltages and duty cycles is equal to (57)By calculating ampere-seconds balance law for the output and VM capacitors, the average current of the power diodes is obtained as (58) 4.4 Number of diode-capacitor VM stages and the turn ratio of the transformer design According to the performed theoretical analysis in a steady state, the voltage stress on the power diodes decreases by increasing the number of diode-capacitor VM stages. Therefore, the design of the VM stages number can be based on the peak inverse voltage of the available power diodes VD−max. Therefore, the number of diode-capacitor VM stages can be obtained as (59)Another important point to design is the design of turn ratio n of the transformer. The voltage stress on the power switches decreases by increasing n. Therefore, the design of n can be done based on the peak inverse voltage of the available power switches VDS−max. By identifying the voltage of output, the value of n can be achieved for the different number of VM stages M as (60) 5 Power losses analysis In this section, the conduction losses of the proposed converter considering the parasitic values of each element such as conductive resistance of power switches (rDS) and diodes (rD), equivalent series resistance (ESR) of the inductors (rL), transformer (primary rLp and secondary rLs) and the capacitors (rC) and forward voltage of diodes (VF) are calculated. For simplicity of calculation, the effect of leakage inductance is neglected and the conduction currents of the elements are approximated by their average values. To calculate the efficiency of the converter, the time intervals [t1, t2], [t3, t4], [t5, t6] and [t7, t8] for the converter operation are ignored. With regards to the first and fifth operation modes [its duration time is (d1 + d2–1)TS], it can be written as (61) (62) (63)As can be seen in (63), the additional conduction losses of the circulating current through the magnetising inductance, capacitor CS and the power switches are very low. However, in order to decrease more these additional losses, the presented converter is more preferred in the application with relatively constant input voltages and low duty cycles. For third operation mode [its duration time is (1 − d2)TS], when S1 is ON and S2 is OFF, can be written as following equations: (64) (65) (66) Moreover, for the seventh operation mode when S1 is OFF and S2 is ON [the duration time is (1 − d2)TS], it can be written as (67) (68) (69) By using the voltage-second balance law for the input inductors L1 and L2, and the magnetising inductance Lm of the transformer, the output voltage by considering the parasitic values for the components can be calculated as follows [see (70) and (71)]. In the presented converter, both the power metal–oxide–semiconductor field-effect transistors (MOSFETs) turn ON under ZCS conditions but they turn OFF under hard switching. Therefore, in the operation modes 4 and 8, the currents through the power MOSFETs S2 and S1 start to rise from zero with smooth slopes, respectively. To calculate the turn ON switching losses, it should calculate the current rising slopes through the power MOSFETs. The current slopes through the MOSFETs S2 and S1 in the fourth and eighth operation modes can be obtained as (70) (71) (72)Therefore, the turn ON switching losses can be calculated as (73) Since the voltage stress values across the power MOSFETs are low, it can be said that the switching turn ON losses are very low and the switching losses are reduced in the converter by ZCS turn ON. Also, with regards to (72), it is obvious that the current slopes of MOSFETs depend on the input voltages and leakage inductor values and it is independent of the input currents. Therefore, the rising current slopes are lower for the higher-voltage gains (for higher selected n and M). In other words, the turn ON switching losses can be more effective for high-voltage gains, low-voltage stresses across the power MOSFETs and higher-output powers (higher-input currents). Calculating the turn OFF switching losses for the power MOSFETs is an important issue and it can be written as (74)Moreover, the stored energy in the output capacitances COSS of the MOSFETs during MOSFETs turn OFF will be internally dissipated in the MOSFETs during turn ON at ZCS, and will significantly contribute to the turn ON losses. The output capacitance loss of the power MOSFETs can be obtained as (75)The converter total switching losses for the MOSFETs S1 and S2 can be written as (76)The core losses of inductors L1 and L2, and the HF transformer can be calculated as
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